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| 8 Bit Microcontroller TLCS-870/C Series TMP86CM27FG TMP86CM27FG The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2006 TOSHIBA CORPORATION All Rights Reserved Page 2 Revision History Date 2006/9/6 2006/9/12 2006/12/18 Revision 1 2 3 First Release Contents Revised Contents Revised Table of Contents TMP86CM27FG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Address Map............................................................................................................................... 9 Program Memory (MaskROM).................................................................................................................. 9 Data Memory (RAM) ............................................................................................................................... 10 Clock Generator...................................................................................................................................... 10 Timing Generator .................................................................................................................................... 12 Operation Mode Control Circuit .............................................................................................................. 13 Single-clock mode Dual-clock mode STOP mode Configuration of timing generator Machine cycle 2.2 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2.1 2.2.2.2 2.2.3.1 2.2.3.2 2.2.3.3 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4 Operating Mode Control ......................................................................................................................... 18 STOP mode IDLE1/2 mode and SLEEP1/2 mode IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) SLOW mode 2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External Reset Input ............................................................................................................................... 31 Address trap reset .................................................................................................................................. 32 Watchdog timer reset.............................................................................................................................. 32 System clock reset.................................................................................................................................. 32 2.3.1 2.3.2 2.3.3 2.3.4 3. Interrupt Control Circuit 3.1 3.2 Interrupt latches (IL19 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt master enable flag (IMF) .......................................................................................................... 36 Individual interrupt enable flags (EF19 to EF4) ...................................................................................... 37 Note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 3.3.2 3.3.3 3.4.1 3.4.2 Interrupt acceptance processing is packaged as follows........................................................................ 39 Saving/restoring general-purpose registers ............................................................................................ 40 Interrupt return ........................................................................................................................................ 41 Using PUSH and POP instructions Using data transfer instructions 3.3.2.1 3.3.2.2 3.2.1 3.2.2 3.4 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Address error detection .......................................................................................................................... 42 Debugging .............................................................................................................................................. 42 i 3.5 3.6 3.7 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. Special Function Register (SFR) 4.1 4.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5. I/O Ports 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Port P0 (P07 to P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P37 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4 (P43 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 53 55 56 58 60 62 65 6. Time Base Timer (TBT) 6.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Configuration .......................................................................................................................................... 67 Control .................................................................................................................................................... 67 Function .................................................................................................................................................. 68 Configuration .......................................................................................................................................... 69 Control .................................................................................................................................................... 69 6.1.1 6.1.2 6.1.3 6.2.1 6.2.2 6.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7. Watchdog Timer (WDT) 7.1 7.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... Selection of Address Trap in Internal RAM (ATAS) ................................................................................ Selection of Operation at Address Trap (ATOUT) .................................................................................. Address Trap Interrupt (INTATRAP)....................................................................................................... Address Trap Reset ................................................................................................................................ 72 73 74 74 75 7.3 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 76 76 76 77 7.3.1 7.3.2 7.3.3 7.3.4 8. 10-Bit Timer/Counter (TC7) 8.1 8.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ii 8.3 8.4 Configuring Control and Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Programmable pulse generator output (PPG output) ............................................................................. 84 50% duty mode Variable duty mode PPG1/PPG2 independent mode 8.4.1.1 8.4.1.2 8.4.1.3 8.4.2.1 8.4.2.2 8.4.2.3 8.4.2.4 8.4.2.5 8.4.3.1 8.4.3.2 8.4.3.3 8.4.4.1 8.4.4.2 8.4.5.1 8.4.5.2 8.4.5.3 8.4.1 8.4.2 Starting a count....................................................................................................................................... 88 Command start and capture mode Command start and trigger start mode Trigger start mode Trigger capture mode (CSTC = 00) Trigger start/stop acceptance mode 8.4.3 Configuring how the timer stops ............................................................................................................. 95 Counting stopped with the outputs initialized Counting stopped with the outputs maintained Counting stopped with the outputs initialized at the end of the period One-time output mode Continuous output mode 8.4.4 8.4.5 One-time/continuous output mode.......................................................................................................... 95 PPG output control (Initial value/output logic, enabling/disabling output) ............................................... 97 Specifying initial values and output logic for PPG outputs Enabling or disabling PPG outputs Using the TC7 as a normal timer/counter 8.4.6 8.4.7 Eliminating noise from the TC7 pin input ................................................................................................ 97 Interrupts................................................................................................................................................. 99 INTTC7T (Trigger start interrupt) INTTC7P (Period interrupt) INTEMG (Emergency output stop interrupt) 8.4.8 8.4.7.1 8.4.7.2 8.4.7.3 8.4.8.1 8.4.8.2 8.4.8.3 8.4.8.4 8.4.8.5 8.4.8.6 Emergency PPG output stop feature .................................................................................................... 100 Enabling/disabling input on the EMG pin Monitoring the emergency PPG output stop state EMG interrupt Canceling the emergency PPG output stop state Restarting the timer after canceling the emergency PPG output stop state Response time between EMG pin input and PPG outputs being initialized 8.4.9 TC7 operation and microcontroller operating mode ............................................................................. 102 9. 8-Bit TimerCounter (TC3, TC4) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8-Bit Timer Mode (TC3 and 4) .............................................................................................................. 8-Bit Event Counter Mode (TC3, 4) ...................................................................................................... 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)................................................................... 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)................................................................ 16-Bit Timer Mode (TC3 and 4) ............................................................................................................ 16-Bit Event Counter Mode (TC3 and 4) .............................................................................................. 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)........................................................ 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ............................................. Warm-Up Counter Mode....................................................................................................................... Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 109 110 110 113 115 116 116 119 121 9.3.9.1 9.3.9.2 10. Real-Time Clock 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Control of the RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 iii 11. Asynchronous Serial interface (UART ) 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 130 Data Receive Operation ..................................................................................................................... 130 131 131 131 132 132 133 125 126 128 129 129 130 130 130 11.8.1 11.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 11.9.1 11.9.2 11.9.3 11.9.4 11.9.5 11.9.6 12. Synchronous Serial Interface (SIO) 12.1 12.2 12.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Clock source ....................................................................................................................................... 138 Shift edge............................................................................................................................................ 139 Leading edge Trailing edge Internal clock External clock 12.3.1.1 12.3.1.2 12.3.2.1 12.3.2.2 12.3.1 12.3.2 12.4 12.5 12.6 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4-bit and 8-bit transfer modes ............................................................................................................. 140 4-bit and 8-bit receive modes ............................................................................................................. 142 8-bit transfer / receive mode ............................................................................................................... 143 12.6.1 12.6.2 12.6.3 13. 10-bit AD Converter (ADC) 13.1 13.2 13.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Software Start Mode ........................................................................................................................... 151 Repeat Mode ...................................................................................................................................... 151 Register Setting ................................................................................................................................ 152 13.4 13.5 13.6 13.3.1 13.3.2 13.3.3 STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 154 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Restrictions for AD Conversion interrupt (INTADC) usage ................................................................. Analog input pin voltage range ........................................................................................................... Analog input shared pins .................................................................................................................... Noise Countermeasure ....................................................................................................................... 155 155 155 155 13.6.1 13.6.2 13.6.3 13.6.4 iv 14. Key-on Wakeup (KWU) 14.1 14.2 14.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15. LCD Driver 15.1 15.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 LCD driving methods .......................................................................................................................... 161 Frame frequency................................................................................................................................. 162 Driving method for LCD driver ............................................................................................................ 163 When using the booster circuit (LCDCR 15.2.1 15.2.2 15.2.3 15.3 15.4 15.2.3.1 15.2.3.2 LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Control Method of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Initial setting ........................................................................................................................................ 167 Store of display data ........................................................................................................................... 167 Example of LCD drive output .............................................................................................................. 170 Display data setting ............................................................................................................................ 165 Blanking .............................................................................................................................................. 166 15.3.1 15.3.2 15.4.1 15.4.2 15.4.3 16. Input/Output Circuitry 16.1 16.2 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 17. Electrical Characteristics 17.1 17.2 17.3 17.4 17.5 17.6 17.7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 180 181 182 183 184 184 18. Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). v vi TMP86CM27FG CMOS 8-Bit Microcontroller TMP86CM27FG Product No. TMP86CM27FG ROM (MaskROM) 32768 bytes RAM 1024 bytes Package P-QFP80-1420-0.80B FLASH MCU TMP86FS27FG Emulation Chip TMP86C927XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) - 132 types & 731 basic instructions 2. 20interrupt sources (External : 7 Internal : 13) 3. Input / Output ports (55 pins) Large current output: 8pins (Typ. 20mA), LED direct drive 4. Prescaler - Time base timer - Divider output function 5. Watchdog Timer 6. 10-bit timer counter: 1ch (2 output pins) 2ports output PPG (Programmed Pulse Generator) 50%duty output mode Variable Duty output mode External-triggered start and stop Emargency stop pin 7. 8-bit timer counter : 2 ch - Timer, Event counter, Programmable divider output (PDO), 060116EBP * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86CM27FG Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 8. 8-bit UART : 1 ch 9. 8-bit SIO: 1 ch 10. 10-bit successive approximation type AD converter - Analog input: 8 ch 11. Key-on wakeup : 4 ch 12. LCD driver/controller Built-in voltage booster for LCD driver With display memory LCD direct drive capability (MAX 40 seg x 4 com) 1/4,1/3,1/2duties or static drive are programmably selectable 13. Clock operation Single clock mode Dual clock mode 14. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz Release by Page 2 1.2 Pin Assignment C1 V1 V2 V3 (SI1) P40 (SO1) P41 (SCK1) P42 (TXD1) P43 (DVO) P30 (TC3/PDO3/PWM3) P31 (TC4/PDO4/PWM4/PPG4) P32 (EMG) P33 (TC7) P34 (PPG1) P35 (PPG2) P36 (RXD1) P37 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET Figure 1-1 Pin Assignment Page 3 (INT5/STOP) P20 AVDD VAREF (STOP5/AIN0) P60 (AIN1) P61 (AIN2) P62 (INT0/AIN3) P63 (STOP2/AIN4) P64 (STOP3/AIN5) P65 (STOP4/AIN6) P66 (AIN7) P67 (RXD0/SEG39) P00 (TXD0/SEG38) P01 (INT1/SEG37) P02 (INT2/SEG36) P03 (INT3/SEG35) P04 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 C0 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 P77 (SEG8) P76 (SEG9) P75 (SEG10) P74 (SEG11) P73 (SEG12) P72 (SEG13) P71 (SEG14) P70 (SEG15) P57 (SEG16) P56 (SEG17) P55 (SEG18) P54 (SEG19) P53 (SEG20) P52 (SEG21) P51 (SEG22) P50 (SEG23) P17 (SEG24) P16 (SEG25) P15 (SEG26) P14 (SEG27) P13 (SEG28) P12(SEG29) P11(SEG30) P10(SEG31) P07(SEG32/SCK0) P06(SEG33/SO0) P05(SEG34/SI0) TMP86CM27FG 1.3 Block Diagram TMP86CM27FG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86CM27FG 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/4) Pin Name P07 SEG32 SCK0 Pin Number Input/Output IO O IO IO O O IO O I IO O I IO O I IO O I IO O O IO O I IO O IO O IO O IO O IO O IO O IO O IO O IO O PORT07 LCD segment output 32 Serial Clock I/O 0 PORT06 LCD segment output 33 Serial Data Output 0 PORT05 LCD segment output 34 Serial Data Input 0 PORT04 LCD segment output 35 External interrupt 3 input PORT03 LCD segment output 36 External interrupt 2 input PORT02 LCD segment output 37 External interrupt 1 input PORT01 LCD segment output 38 UART data output 0 PORT00 LCD segment output 39 UART data input 0 PORT17 LCD segment output 24 PORT16 LCD segment output 25 PORT15 LCD segment output 26 PORT14 LCD segment output 27 PORT13 LCD segment output 28 PORT12 LCD segment output 29 PORT11 LCD segment output 30 PORT10 LCD segment output 31 Functions 27 P06 SEG33 SO0 P05 SEG34 SI0 P04 SEG35 INT3 P03 SEG36 INT2 P02 SEG37 INT1 P01 SEG38 TXD0 P00 SEG39 RXD0 P17 SEG24 P16 SEG25 P15 SEG26 P14 SEG27 P13 SEG28 P12 SEG29 P11 SEG30 P10 SEG31 P22 XTOUT 26 25 24 23 22 21 20 35 34 33 32 31 30 29 28 7 PORT22 Resonator connecting pins(32.768kHz) for inputting external clock PORT21 Resonator connecting pins(32.768kHz) for inputting external clock P21 XTIN 6 IO I Page 5 1.4 Pin Names and Functions TMP86CM27FG Table 1-1 Pin Names and Functions(2/4) Pin Name P20 STOP INT5 Pin Number Input/Output IO I I IO I IO O IO O IO I IO I IO O I IO O I IO O IO O IO IO IO O IO I IO O IO O IO O IO O IO O IO O IO O IO O IO I Functions PORT20 STOP mode release signal input External interrupt 5 input PORT37 UART data input 1 PORT36 Timer counter 7 PPG2 output PORT35 Timer counter 7 PPG1 output PORT34 Timer counter 7 input PORT33 Timer counter 7 Emergency stop input PORT32 PDO4/PWM4/PPG4 output TC4 input PORT31 PDO3/PWM3 output TC3 input PORT30 Divider Output PORT43 UART data output 1 PORT42 Serial Clock I/O 1 PORT41 Serial Data Output 1 PORT40 Serial Data Input 1 PORT57 LCD segment output 16 PORT56 LCD segment output 17 PORT55 LCD segment output 18 PORT54 LCD segment output 19 PORT53 LCD segment output 20 PORT52 LCD segment output 21 PORT51 LCD segment output 22 PORT50 LCD segment output 23 PORT67 Analog Input7 9 P37 RXD1 P36 PPG2 P35 PPG1 P34 TC7 P33 EMG 80 79 78 77 76 P32 PDO4/PWM4/PPG4 75 TC4 P31 PDO3/PWM3 74 TC3 P30 DVO 73 P43 TXD1 P42 SCK1 72 71 P41 SO1 P40 SI1 P57 SEG16 P56 SEG17 P55 SEG18 P54 SEG19 P53 SEG20 P52 SEG21 P51 SEG22 P50 SEG23 P67 AIN7 70 69 43 42 41 40 39 38 37 36 19 Page 6 TMP86CM27FG Table 1-1 Pin Names and Functions(3/4) Pin Name P66 AIN6 STOP4 P65 AIN5 STOP3 P64 AIN4 STOP2 P63 AIN3 INT0 Pin Number Input/Output IO I I IO I I IO I I IO I I IO I IO I IO I I IO O IO O IO O IO O IO O IO O IO O IO O O O O O O O O O O O PORT66 Analog Input6 STOP4 input PORT65 Analog Input5 STOP3 input PORT64 Analog Input4 STOP2 input PORT63 Analog Input3 External interrupt 0 input PORT62 Analog Input2 PORT61 Analog Input1 PORT60 Analog Input0 STOP5 input PORT77 LCD segment output 8 PORT76 LCD segment output 9 PORT75 LCD segment output 10 PORT74 LCD segment output 11 PORT73 LCD segment output 12 PORT72 LCD segment output 13 PORT71 LCD segment output 14 PORT70 LCD segment output 15 LCD segment output 7 LCD segment output 6 LCD segment output 5 LCD segment output 4 LCD segment output 3 LCD segment output 2 LCD segment output 1 LCD segment output 0 LCD common output 3 LCD common output 2 Functions 18 17 16 15 P62 AIN2 P61 AIN1 P60 AIN0 STOP5 P77 SEG8 P76 SEG9 P75 SEG10 P74 SEG11 P73 SEG12 P72 SEG13 P71 SEG14 P70 SEG15 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 14 13 12 51 50 49 48 47 46 45 44 52 53 54 55 56 57 58 59 63 62 Page 7 1.4 Pin Names and Functions TMP86CM27FG Table 1-1 Pin Names and Functions(4/4) Pin Name COM1 COM0 V3 V2 V1 C1 C0 XIN XOUT RESET Pin Number 61 60 68 67 66 65 64 2 3 8 4 11 10 5 1 Input/Output O O I I I I I I O I I I I I I LCD common output 1 LCD common output 0 LCD voltage booster pin LCD voltage booster pin LCD voltage booster pin LCD voltage booster pin LCD voltage booster pin Functions Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock Reset signal Test pin for out-going test. Normally, be fixed to low. Analog Base Voltage Input Pin for A/D Conversion Analog Power Supply +5V 0(GND) TEST VAREF AVDD VDD VSS Page 8 TMP86CM27FG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86CM27FG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the memory address map. TMP86CM27FG 0000H SFR 003FH 0040H 64 bytes SFR: RAM 043FH 0F80H 1024 bytes RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack DBR: DBR 0FFFH 8000H 128 bytes Data buffer register includes: Peripheral control registers Peripheral status registers LCD display memory MaskROM: Program memory MaskROM FFB0H FFBFH FFC0H FFDFH FFE0H FFFFH 32768 bytes Vector table for interrupts (16 bytes) Vector table for vector call instructions (32 bytes) Vector table for interrupts (32 bytes) Figure 2-1 Memory Address Map 2.1.2 Program Memory (MaskROM) The TMP86CM27FG has a 32768 bytes (Address 8000H to FFFFH) of program memory (MaskROM ). Page 9 2. Operational Description 2.2 System Clock Controller TMP86CM27FG 2.1.3 Data Memory (RAM) The TMP86CM27FG has 1024bytes (Address 0040H to 043FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to "00H". (TMP86CM27FG) LD LD LD SRAMCLR: LD INC DEC JRS HL, 0040H A, H BC, 03FFH (HL), A HL BC F, SRAMCLR ; Start address setup ; Initial value (00H) setup 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register Clock generator XIN fc TBTCR 0036H High-frequency clock oscillator XOUT XTIN Timing generator fs Standby controller 0038H SYSCR1 0039H SYSCR2 Low-frequency clock oscillator XTOUT System clocks Clock generator control System control registers Figure 2-2 System Colck Control 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Page 10 TMP86CM27FG High-frequency clock XIN XOUT XIN XOUT (Open) XTIN Low-frequency clock XTOUT XTIN XTOUT (Open) (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. Page 11 2. Operational Description 2.2 System Clock Controller TMP86CM27FG 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode 7. LCD 2.2.2.1 Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2 fc or fs Main system clock generator SYSCK DV7CK Machine cycle counters High-frequency clock fc Low-frequency clock fs 12 fc/4 S A 123456 B Y Divider 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S B0 B1 A0 Y0 A1 Y1 Multiplexer Multiplexer Warm-up controller Watchdog timer Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) Figure 2-4 Configuration of Timing Generator Page 12 TMP86CM27FG Timing Generator Control Register TBTCR (0036H) 7 (DVOEN) 6 (DVOCK) 5 4 DV7CK 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DV7CK Selection of input to the 7th stage of the divider 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. 2.2.3.1 Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86CM27FG is placed in this mode after reset. Page 13 2. Operational Description 2.2 System Clock Controller TMP86CM27FG (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2 2.2.3.2 Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2 Page 14 TMP86CM27FG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2 2.2.3.3 STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 15 2. Operational Description 2.2 System Clock Controller TMP86CM27FG IDLE0 mode Reset release RESET IDLE1 mode (a) Single-clock mode Note 2 SYSCR2 IDLE2 mode Interrupt NORMAL2 mode SYSCR2 SLEEP1 mode (b) Dual-clock mode SYSCR2 Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Oscillator Operating Mode High Frequency Low Frequency CPU Core TBT Other Peripherals Reset Operate 4/fc [s] Machine Cycle Time RESET NORMAL1 Single clock IDLE1 IDLE0 STOP NORMAL2 IDLE2 SLOW2 Dual clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Oscillation Stop Oscillation Reset Operate Stop Halt Reset Operate Halt Operate with high frequency Halt - 4/fc [s] Oscillation Halt Operate with low frequency Halt Operate with low frequency Operate Operate 4/fs [s] Halt Halt Halt - Page 16 TMP86CM27FG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP RELM RETM OUTEN STOP mode start Release method for STOP mode Operating mode after STOP mode Port output during STOP mode 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) 0: Edge-sensitive release 1: Level-sensitive release 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode 0: High impedance 1: Output kept Return to NORMAL mode Return to SLOW mode 3 x 213/fs 213/fs 3 x 26/fs 26/fs R/W R/W R/W R/W WUT Warm-up time at releasing STOP mode 00 01 10 11 3 x 216/fc 216/fc 3 x 214/fc 214/fc R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause external interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H) 7 XEN 6 XTEN 5 SYSCK 4 IDLE 3 2 TGHALT 1 0 (Initial value: 1000 *0**) XEN XTEN High-frequency oscillator control Low-frequency oscillator control Main system clock select (Write)/main system clock monitor (Read) CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) TG control (IDLE0 and SLEEP0 modes) 0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) R/W R/W SYSCK IDLE TGHALT Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator, *; Don't care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR Page 17 2. Operational Description 2.2 System Clock Controller TMP86CM27FG 2.2.4 Operating Mode Control STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 2.2.4.1 Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2). However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to STOP2 pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5 to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low or STOP5 to STOP2 input is high. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: TEST JRS DI SET (SYSCR1). 7 (SYSCR1), 01010000B (P2PRD). 0 F, SSTOPH ; IMF 0 ; Starts STOP mode ; Sets up the level-sensitive release mode ; Wait until the STOP pin input goes low level Page 18 TMP86CM27FG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD DI SET SINT5: RETI (SYSCR1). 7 (P2PRD). 0 F, SINT5 (SYSCR1), 01010000B ; To reject noise, STOP mode does not start if port P20 is at high ; Sets up the level-sensitive release mode. ; IMF 0 ; Starts STOP mode STOP pin XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. VIH Warm up NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode. Example :Starting STOP mode from NORMAL mode DI LD (SYSCR1), 10010000B ; IMF 0 ; Starts after specified to the edge-sensitive release mode STOP pin XOUT pin NORMAL operation STOP mode started by the program. STOP operation VIH Warm up NORMAL operation STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode Page 19 2. Operational Description 2.2 System Clock Controller TMP86CM27FG STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1 Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 12.288 4.096 3.072 1.024 Return to SLOW Mode 750 250 5.85 1.95 Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 20 Turn off Oscillator circuit Turn on Main system clock a+3 SET (SYSCR1). 7 n+1 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+2 n+3 n+4 Halt Program counter a+2 Instruction execution Divider n 0 Figure 2-9 STOP Mode Start/Release a+4 Instruction address a + 2 Page 21 0 1 (b) STOP mode release Warm up STOP pin input Oscillator circuit Turn off Turn on Main system clock a+5 Instruction address a + 3 Program counter a+3 a+6 Instruction address a + 4 Instruction execution Halt Divider 0 Count up 2 3 TMP86CM27FG 2. Operational Description 2.2 System Clock Controller TMP86CM27FG 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input No No Interrupt request Yes "0" IMF Reset Normal release mode "1" (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 22 TMP86CM27FG * Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2 Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 23 Main system clock 2.2 System Clock Controller 2. Operational Description Interrupt request a+2 SET (SYSCR2). 4 Operate Halt a+3 Program counter Instruction execution Watchdog timer (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Main system clock Interrupt request a+3 Instruction address a + 2 Operate Normal release mode a+4 Program counter Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 24 a+3 Acceptance of interrupt Operate Operate Interrupt release mode Instruction execution Halt Watchdog timer Halt Main system clock Interrupt request Program counter Instruction execution Halt Watchdog timer Halt TMP86CM27FG (b) IDLE1/2 and SLEEP1/2 modes release TMP86CM27FG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0, SLEEP0 modes by instruction CPU and WDT are halted Reset input No No TBT source clock falling edge Yes TBTCR Yes Reset No No (Normal release mode) Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes Page 25 2. Operational Description 2.2 System Clock Controller TMP86CM27FG * Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2 Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR (1) Normal release mode (IMF*EF7*TBTCR (2) Interrupt release mode (IMF*EF7*TBTCR Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR Page 26 Main system clock Interrupt request a+2 a+3 Program counter Instruction execution SET (SYSCR2). 2 Halt Watchdog timer Operate (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a Main system clock TBT clock a+3 a+4 Program counter Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 27 Instruction address a + 2 Operate Normal release mode a+3 Instruction execution Halt Watchdog timer Halt Main system clock TBT clock Program counter Instruction execution Halt Acceptance of interrupt Operate Interrupt release mode (b) IDLE and SLEEP0 modes release TMP86CM27FG Watchdog timer Halt 2. Operational Description 2.2 System Clock Controller TMP86CM27FG 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET LD LD LDW DI SET EI SET : PINTTC4: CLR SET (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 28 TMP86CM27FG (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note: After SYSCK is cleared to "0", executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET LD LD LD DI SET EI SET : PINTTC4: CLR CLR (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 29 2.2 System Clock Controller 2. Operational Description Highfrequency clock Lowfrequency clock Main system clock Turn off SYSCK XEN CLR (SYSCR2). 7 SLOW2 mode (a) Switching to the SLOW mode Instruction execution SET (SYSCR2). 5 NORMAL2 mode SLOW1 mode Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 30 CLR (SYSCR2). 5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode Highfrequency clock Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2). 7 TMP86CM27FG SLOW1 mode NORMAL2 mode TMP86CM27FG 2.3 Reset Circuit The TMP86CM27FG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5s at 16.0 MHz) when power is turned on. Table 2-3 shows on-chip hardware initialization by reset action. Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Program counter Stack pointer General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL) (PC) (SP) Initial Value (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Output latches of I/O ports Not initialized Not initialized 0 0 Control registers 0 LCD data buffer RAM Refer to each of control register Not initialized Not initialized Refer to I/O port circuitry Watchdog timer Enable Prescaler and divider of timing generator 0 On-chip Hardware Initial Value 2.3.1 External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2-15 Reset Circuit Page 31 2. Operational Description 2.3 Reset Circuit TMP86CM27FG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. Instruction execution Internal reset JP a Address trap is occurred Reset release Instruction at address r maximum 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is in the SFR, DBR or on-chip RAM (WDTCR1 Figure 2-16 Address Trap Reset 2.3.3 Watchdog timer reset Refer to Section "Watchdog Timer". 2.3.4 System clock reset If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2 Page 32 TMP86CM27FG Page 33 2. Operational Description 2.3 Reset Circuit TMP86CM27FG Page 34 TMP86CM27FG 3. Interrupt Control Circuit The TMP86CM27FG has a total of 20 interrupt sources excluding reset. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Latch - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 Vector Address FFFE FFFC FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFEE FFEC FFEA FFE8 FFE6 FFE4 FFE2 FFE0 FFBE FFBC FFBA FFB8 FFB6 FFB4 FFB2 FFB0 Interrupt Factors Internal/External Internal Internal Internal Internal External External External Internal External External Internal Internal Internal Internal Internal Internal External Internal Internal External (Reset) INTSWI (Software interrupt) INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT (Watchdog timer interrupt) INTEMG INT0 Enable Condition Non-maskable Non-maskable Non-maskable Non-maskable Non-maskable IMF* EF4 = 1 IMF* EF5 = 1, INT0EN = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1 IMF* EF9 = 1 IMF* EF10 = 1 IMF* EF11 = 1 IMF* EF12 = 1 IMF* EF13 = 1 IMF* EF14 = 1 IMF* EF15 = 1 IMF* EF16 = 1 IMF* EF17 = 1 IMF* EF18 = 1 IMF* EF19 = 1 IMF* EF20 = 1 IMF* EF21 = 1 IMF* EF22 = 1 IMF* EF23 = 1 Priority 1 2 2 2 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 INT1 INTTBT INT2 INTTC7T INTRXD INTSIO INTTXD INTTC4 INTTC7P INTADC INT3 INTTC3 INTRTC INT5 Reserved Reserved Reserved Reserved Note 1: To use the address trap interrupt (INTATRAP), clear WDTCR1 3.1 Interrupt latches (IL19 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. Page 35 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CM27FG The interrupt latches are located on address 002EH, 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LDW EI (ILL), 1110100000111111B ; IMF 0 ; IL12, IL10 to IL6 0 ; IMF 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ILH, A ILL Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 002CH, 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". Page 36 TMP86CM27FG 3.2.2 Individual interrupt enable flags (EF19 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF19 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI ; IMF 1 (EIRL), 1110100010100000B ; IMF 0 ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); /* 3AH shows EIRL address */ Page 37 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CM27FG Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) ILL (003CH) (Initial value: ****0000) ILE (002EH) 7 - 6 - 5 - 4 - 3 IL19 2 IL18 1 IL17 0 IL16 ILE (002EH) IL19 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 00000000 0000***0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 EF14 13 EF13 12 EF12 11 EF11 10 EF10 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 EIRL (003AH) 3 2 1 0 IMF EIRH (003BH) (Initial value: ****0000) EIRE (002CH) 7 - 6 - 5 - 4 - 3 EF19 2 EF18 1 EF17 0 EF16 EIRE (002CH) EF19 to EF4 IMF Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 38 TMP86CM27FG 3.3 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 s @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. 1-machine cycle Interrupt service task Interrupt request Interrupt latch (IL) IMF Execute instruction a-1 Execute instruction Execute instruction Interrupt acceptance Execute RETI instruction PC a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address Interrupt service program FFF0H FFF1H 03H D2H Vector D203H D204H 0FH 06H Figure 3-2 Vector table address,Entry address Page 39 3. Interrupt Control Circuit 3.3 Interrupt Sequence TMP86CM27FG A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers. 3.3.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP A SP PCL PCH PSW At acceptance of an interrupt W PCL PCH PSW At execution of PUSH instruction SP PCL PCH PSW At execution of POP instruction SP b-5 b-4 b-3 b-2 b-1 b At execution of RETI instruction Figure 3-3 Save/store register using PUSH and POP instructions 3.3.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Page 40 TMP86CM27FG Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; RETURN Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP LD PUSH WA WA, Return Address WA ; Recover SP by 2 ; ; Alter stacked data (interrupt processing) RETN ; RETURN Page 41 3. Interrupt Control Circuit 3.4 Software Interrupt (INTSW) TMP86CM27FG Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC INC INC SP SP SP ; Recover SP by 3 ; ; (interrupt processing) LD JP EIRL, data Restart Address ; Set IMF to "1" or clear it to "0" ; Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging. 3.4.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM, DBR or SFR areas. 3.4.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.5 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 3.6 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). Page 42 TMP86CM27FG 3.7 External Interrupts The TMP86CM27FG has 7 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT3. The INT0/P63 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P63 pin function selection are performed by the external interrupt control register (EINTCR). Source Pin Enable Conditions Release Edge Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT0 INT0 IMF EF5 INT0EN=1 Falling edge INT1 INT1 IMF EF6 = 1 Falling edge or Rising edge INT2 INT2 IMF EF8 = 1 Falling edge or Rising edge INT3 INT3 IMF EF16 = 1 Falling edge or Rising edge INT5 INT5 IMF EF19 = 1 Falling edge Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL5 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Page 43 3. Interrupt Control Circuit 3.7 External Interrupts TMP86CM27FG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 4 3 INT3ES 2 INT2ES 1 INT1ES 0 (Initial value: 00** 000*) INT1NC INT0EN INT3 ES INT2 ES INT1 ES Noise reject time select P63/INT0 pin configuration INT3 edge select INT2 edge select INT1 edge select 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P63 input/output port 1: INT0 pin (Port P63 should be set to an input mode) 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge R/W R/W R/W R/W R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Page 44 TMP86CM27FG 4. Special Function Register (SFR) The TMP86CM27FG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP86CM27FG. 4.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H ADCDR2 ADCDR1 P4PRD P5PRD P7PRD UARTSR P2PRD P3PRD TC3CR TC4CR PWREG3 PWREG4 TTREG3 TTREG4 Reserved Reserved UARTCR1 Read P0DR P1DR P2DR P3DR P4DR P5DR P6DR P7DR TC7DRAL TC7DRAH TC7DRBL TC7DRBH TC7DRCL TC7DRCH ADCCR1 ADCCR2 P0CR P1CR P3OUTCR P4OUTCR P6CR1 P6CR2 Write Page 45 4. Special Function Register (SFR) 4.1 SFR TMP86CM27FG Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read Reserved LCDCR TC7CR1 TC7CR2 TC7CR3 EIRE RTCCR ILE Reserved Reserved Reserved Reserved Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH Reserved PSW Write UARTCR2 WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 46 TMP86CM27FG 4.2 DBR Address 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H 0F8AH 0F8BH 0F8CH 0F8DH 0F8EH 0F8FH 0F90H 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH Read SEG1/0 SEG3/2 SEG5/4 SEG7/6 SEG9/8 SEG11/10 SEG13/12 SEG15/14 SEG17/16 SEG19/18 SEG21/20 SEG23/22 SEG25/24 SEG27/26 SEG29/28 SEG31/30 SEG33/32 SEG35/34 SEG37/36 SEG39/38 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Write Page 47 4. Special Function Register (SFR) 4.2 DBR TMP86CM27FG Address 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H 0FA7H 0FA8H 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H 0FB7H 0FB8H 0FB9H 0FBAH 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH Read SIOBR0 SIOBR1 SIOBR2 SIOBR3 SIOBR4 SIOBR5 SIOBR6 SIOBR7 SIOSR RDBUF P0LCR P1LCR P5LCR P7LCR TC7DRDL TC7DRDH TC7DREL TC7DREH TC7CAPAL TC7CAPAH TC7CAPBL TC7CAPBH Reserved Reserved Reserved MULSEL Reserved Reserved Reserved Reserved Write SIOCR1 SIOCR2 STOPCR TDBUF - Address 0FC0H :: 0FDFH Read Reserved :: Reserved Write Address 0FE0H :: 0FFFH Read Reserved :: Reserved Write Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 48 TMP86CM27FG 5. I/O Ports The TMP86CM27FG have 8 parallel input/output ports (55 pins) as follows. Primary Function Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 8-bit I/O port 8-bit I/O port 3-bit I/O port 8-bit I/O port 4-bit I/O port 8-bit I/O port 8-bit I/O port 8-bit I/O port Secondary Functions LCD segment output. External interrupt, serial interface input/output and UART input/output. LCD segment output. Low-frequency resonator connections, external interrupt input, STOP mode release signal input. Timer/counter input/output, UART input and divider output. Serial interface input/output and UART output. LCD segment output. Analog input, external interrupt input and STOP mode release signal input. LCD segment output. Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. Figure 5-1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. Fetch cycle S0 S1 S2 S3 Fetch cycle S0 S1 S2 S3 Read cycle S0 S1 S2 S3 Instruction execution cycle Example: LD A, (x) Input strobe Data input (a) Input timing Fetch cycle S0 S1 S2 S3 Fetch cycle S0 S1 S2 S3 Write cycle S0 S1 S2 S3 Instruction execution cycle Example: LD (x), A Output strobe Old (b) Output timing New Data output Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 5-1 Input/Output Timing (Example) Page 49 5. I/O Ports 5.1 Port P0 (P07 to P00) TMP86CM27FG 5.1 Port P0 (P07 to P00) Port P0 is an 8-bit input/output port which can be configured as an input or an output in 1-bit unit. Port P0 is also used as a UART input/output, an external interrupt input, serial interface input/output and segment output of LCD. Input/output mode is specified by the P0 control register (P0CR). When used as an input port or a secondary function input pins (UART input, external interrupt input or serial interface input), the corresponding bit of P0CR and P0LCR should be cleared to "0". When used as an output port, the corresponding bit of P0CR should be set to "1", and the respective P0LCR bit should be cleared to "0". When used as an UART output pin, or serial interface output pin, the corresponding bit of P0CR and the output latch (P0DR) should be set to "1", and the respective P0LCR bit should be cleared to "0". When used as a segment pins of LCD, the respective bit of P0LCR should be set to "1". During reset, the P0DR, P0CR and P0LCR are initialized to "0". When the bit of P0CR and P0LCR is "0", the corresponding bit data by read instruction is a terminal input data. When the bit of P0CR is "0" and that of P0LCR is "1", the corresponding bit data by read instruction is always "0". When the bit of P0CR is "1", the corresponding bit data by read instruction is the value of P0DR. Table 5-1 Register Programming for Multi-function Ports Programmed Value Function P0DR Port input, UART input, serial interface input, and external interrupt input Port "0" output Port "1" output, UART output and serial interface output LCD segment output * "0" "1" * P0CR "0" "1" "1" * P0LCR "0" "0" "0" "1" Note: Asterisk (*) indicates "1" or "0" either of which can be selected. Table 5-2 Values Read from P0DR and Register Programming Conditions Values Read from P0DR P0CR "0" "0" "1" "1" P0LCR "0" "1" "0" Output latch contents Terminal input data "0" Page 50 TMP86CM27FG STOP OUTEN P0LCRi input P0LCRi P0CRi input P0CRi D Q D Q Data input (P0DRi) Data output (P0DRi) D Q P0i Output latch LCD data output Note: i = 7 to 0 Figure 5-2 Port 0 7 P0DR (0000H) R/W P07 SEG32 SCK0 6 P06 SEG33 SO0 5 P05 SEG34 SI0 4 P04 SEG35 INT3 3 P03 SEG36 INT2 2 P02 SEG37 INT1 1 P01 SEG38 TXD0 0 P00 SEG39 RXD0 (Initial value: 0000 0000) P0LCR (0FACH) (Initial value: 0000 0000) P0LCR Port P0/segment output control (Set for each bit individually) 0:P0 input/output port or secondary function (excect for segment) 1: LCD segment output R/W P0CR (0010H) (Initial value: 0000 0000) P0CR P0 port input/output control (Set for each bit individually) 0: Input mode 1: Output mode R/W Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. Multi function register 7 MULSEL (0FBBH) SIOSEL UARTSEL SIO function pins select UART function pins select 6 5 4 3 2 1 SIOSEL 0 UARTSEL (Initial value: **** **00) 0: P05(SI0), P06(SO0), P07(SCK0) 1: P40(SI1), P41(SO1), P42(SCK1) 0: P01(TXD0), P00(RXD0) 1: P43(TXD1), P37(RXD1) R/W Note 1: Do not change a terminal during operation. Page 51 5. I/O Ports 5.1 Port P0 (P07 to P00) TMP86CM27FG Note 2: Perform the setting terminal of a port after performing a setup by MULSEL, when changing a terminal. Page 52 TMP86CM27FG 5.2 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port which can be configured as an input or an output in 1-bit unit. Port P1 is also used as a segment output of LCD. Input/output mode is specified by the P1 control register (P1CR). When used as an input port, the corresponding bit of P1CR and P1LCR should be cleared to "0". When used as an output port, the corresponding bit of P1CR should be set to "1", and the respective P1LCR bit should be cleared to "0". When used as a segment pins of LCD, the respective bit of P1LCR should be set to "1". During reset, the output latch (P1DR), P1CR and P1LCR are initialized to "0". When the bit of P1CR and P1LCR is "0", the corresponding bit data by read instruction is a terminal input data. When the bit of P1CR is "0" and that of P1LCR is "1", the corresponding bit data by read instruction is always "0". When the bit of P1CR is "1", the corresponding bit data by read instruction is the value of P1DR. Table 5-3 Register Programming for Multi-function Ports Programmed Value Function P1DR Port input Port "0" output Port "1" output LCD segment output * "0" "1" * P1CR "0" "1" "1" * P1LCR "0" "0" "0" "1" Note: Asterisk (*) indicates "1" or "0" either of which can be selected. Table 5-4 Values Read from P1DR and Register Programming Conditions Values Read from P1DR P1CR "0" "0" "1" "1" P1LCR "0" "1" "0" Output latch contents Terminal input data "0" Page 53 5. I/O Ports 5.2 Port P1 (P17 to P10) TMP86CM27FG STOP OUTEN P1LCRi input P1LCRi P1CRi input P1CRi D Q D Q Data input (P1DRi) Data output (P1DRi) D Q P1i Output latch LCD data output Note: i = 7 to 0 Figure 5-3 Port 1 P1DR (0001H) R/W 7 P17 SEG24 6 P16 SEG25 5 P15 SEG26 4 P14 SEG27 3 P13 SEG28 2 P12 SEG29 1 P11 SEG30 0 P10 SEG31 (Initial value: 0000 0000) P1LCR (0FADH) (Initial value: 0000 0000) P1LCR Port P1/segment output control (Set for each bit individually) 0: P1 input/output port 1: LCD segment output R/W P1CR (0011H) (Initial value: 0000 0000) P1CR P1 port input/output control (Set for each bit individually) 0: Input mode 1: Output mode R/W Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. Page 54 TMP86CM27FG 5.3 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set to "1". During reset, the P2DR is initialized to "1". A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dualclock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports. It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address. When read the output latch data, the P2DR should be read and when read the terminal input data, the P2PRD register should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable. Data input (P20PRD) Data input (P20) Data output (P20) Contorl input Data input (P21PRD) Output latch read (P21) Data output (P21) Data input (P22PRD) Output latch read (P22) Data output (P22) D Q D Q D Q P20 (INT5, STOP) Output latch Osc. enable P21 (XTIN) Output latch P22 (XTOUT) Output latch STOP OUTEN XTEN fs Figure 5-4 Port 2 P2DR (0002H) R/W 7 6 5 4 3 2 P22 XTOUT 1 P21 XTIN 0 P20 INT5 STOP (Initial value: **** *111) P2PRD (0F9CH) Read only P22 P21 P20 Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes high-Z mode. Page 55 5. I/O Ports 5.4 Port P3 (P37 to P30) TMP86CM27FG 5.4 Port P3 (P37 to P30) Port P3 is a 8-bit input/output port. It is also used as a timer/counter input/output or divider output. When used as a timer/counter output or divider output, respective output latch (P3DR) should be set to "1". It can be selected whether output circuit of port P3 is C-MOS output or a sink open drain individually, by setting P3OUTCR. When a corresponding bit of P3OUTCR is "0", the output circuit is selected to a sink open drain and when a corresponding bit of P3OUTCR is "1", the output circuit is selected to a C-MOS output. When used as an input port or timer/counter input, respective output control (P3OUTCR) should be set to "0" after P3DR is set to "1". When using this port as a PPG1 and/or PPG2 output, set the output latch (P3DR) and then set the P3OUTCR to "1". Next, set the PPG output initial value in the PPG1INI and/or PPG2INI, and set the PPG1OE and/or PPG2OE to "1" to enable PPG output. At this time, the output latch (P3DR) should be set to the same value as the PPG output initial value (PPG1INI, PPG2INI). During reset, the P3DR is initialized to "1", and the P3OUTCR is initialized to "0". P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address. When read the output latch data, the P3DR should be read and when read the terminal input data, the P3PRD register should be read. STOP OUTEN P3OUTCRi P3OUTCRi input Data input (P3PRD) Output latch read (P3DR) Data output (P3DR) Control output Control input a) P37, P34, P33, P32, P31, P30 D Q D Q P3i Output latch Note: i = 4 to 0 and 7 STOP OUTEN P3OUTCRj P3OUTCRj Data input (P3PRD) Data latch read (P3DR) Data output (P3DR) PPGk PPGkINI PPGkOE b) P36, P35 D Q A D Q P3i Output latch B S Note: j = 6, 5 k = 2, 1 Figure 5-5 Port 3 Page 56 TMP86CM27FG 7 P3DR (0003H) R/W P37 RXD1 6 P36 PPG2 5 P35 PPG1 4 P34 TC7 3 P33 EMG 2 P32 PWM4 PDO4 PPG4 1 P31 PWM3 PDO3 0 P30 DVO (Initial value: 1111 1111) TC3 TC4 P3OUTCR (0012H) (Initial value: 0000 0000) P3OUTCR Port P3 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: C-MOS output R/W P3PRD (0017H) Read only P37 P36 P35 P34 P33 P32 P31 P30 Multi function register 7 MULSEL (0FBBH) SIOSEL UARTSEL SIO function pins select UART function pins select 6 5 4 3 2 1 SIOSEL 0 UARTSEL (Initial value: **** **00) 0: P05(SI0), P06(SO0), P07(SCK0) 1: P40(SI1), P41(SO1), P42(SCK1) 0: P01(TXD0), P00(RXD0) 1: P43(TXD1), P37(RXD1) R/W Note 1: Do not change a terminal during operation. Note 2: Perform the setting terminal of a port after performing a setup by MULSEL, when changing a terminal. Page 57 5. I/O Ports 5.5 Port P4 (P43 to P40) TMP86CM27FG 5.5 Port P4 (P43 to P40) Port P4 is a 4-bit input/output port. It is also used as a UART output or serial interface input/output. When used as a UART output or serial interface output, respective output latch (P4DR) should be set to "1". It can be selected whether output circuit of port P4 is C-MOS output or a sink open drain individually, by setting P4OUTCR. When a corresponding bit of P4OUTCR is "0", the output circuit is selected to a sink open drain and when a corresponding bit of P4OUTCR is "1", the output circuit is selected to a C-MOS output. When used as an input port or serial interface input, respective output control (P4OUTCR) should be set to "0" after P4DR is set to "1". During reset, the P4DR is initialized to "1", and the P4OUTCR is initialized to "0". P4 port output latch (P4DR) and P4 port terminal input (P4PRD) are located on their respective address. When read the output latch data, the P4DR should be read and when read the terminal input data, the P4PRD register should be read. If a read instruction is executed for the P4PRD, P4DR and the P4OUTCR, read data of bits 7 to 5 are unstable. Table 5-5 Register Programming for Multi-function Ports (P43 to P40) Programmed Value Function P4DR Port input or timer counter input Port "0" output Port "1" output or timer counter output "1" "0" "1" P4OUTCR "0" Programming for each applications STOP OUTEN P4OUTCRi P4OUTCRi input Data input (P4PRD) Output latch read (P4DR) Data output (P4DR) Control output Control input Note: i = 4 to 0 D Q D Q P4i Output latch Figure 5-6 Port 4 Page 58 TMP86CM27FG P4DR (0004H) R/W 7 6 5 4 3 P43 TXD1 2 P42 SCK1 1 P41 SO1 0 P40 SI1 (Initial value: **** 1111) P4OUTCR (0013H) (Initial value: **** 0000) P4OUTCR Port P4 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: C-MOS output R/W P4PRD (0022H) Read only P43 P42 P41 P40 Multi function register 7 MULSEL (0FBBH) SIOSEL UARTSEL SIO function pins select UART function pins select 6 5 4 3 2 1 SIOSEL 0 UARTSEL (Initial value: **** **00) 0: P05(SI0), P06(SO0), P07(SCK0) 1: P40(SI1), P41(SO1), P42(SCK1) 0: P01(TXD0), P00(RXD0) 1: P43(TXD1), P37(RXD1) R/W Note 1: Do not change a terminal during operation. Note 2: Perform the setting terminal of a port after performing a setup by MULSEL, when changing a terminal. Page 59 5. I/O Ports 5.6 Port P5 (P57 to P50) TMP86CM27FG 5.6 Port P5 (P57 to P50) Port P5 is an 8-bit input/output port which can be configured as an input or an output in 1-bit unit. Port P5 is also used as a segment output of LCD. When used as an input port, the corresponding bit of P5LCR should be cleared to "0", and the respective P5DR bit should be set to "1". When used as an output port, the respective P5LCR bit should be cleared to "0". When used as a segment pins of LCD, the respective bit of P5LCR should be set to "1". During reset, the output latch (P5DR) are intialized to "1", and P5LCR are initialized to "0". P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address. When read the output latch data, the P5DR should be read and when read the terminal input data, the P5PRD register should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is read. Table 5-6 Register Programming for Multi-function Ports Programmed Value Function P5DR Port input Port "0" output LCD segment output "1" "0" * P5LCR "0" "0" "1" Note: Asterisk (*) indicates "1" or "0" either of which can be selected. STOP OUTEN P5LCRi P5CRi input D Q Terminal input (P5PRD) Output latch data (P5DRi) Data output (P5DR) D Q P5i Output latch LCD data output Note: i = 7 to 0 Figure 5-7 Port 5 Page 60 TMP86CM27FG P5DR (0005H) R/W 7 P57 SEG16 6 P56 SEG17 5 P55 SEG18 4 P54 SEG19 3 P53 SEG20 2 P52 SEG21 1 P51 SEG22 0 P50 SEG23 (Initial value: 1111 1111) P5LCR (0FAEH) (Initial value: 0000 0000) P5LCR Port P5/segment output control (Set for each bit individually) 0: P5 input/output port 1: LCD segment output R/W P5PRD (0023H) Read only P57 P56 P55 P54 P53 P52 P51 P50 Page 61 5. I/O Ports 5.7 Port P6 (P67 to P60) TMP86CM27FG 5.7 Port P6 (P67 to P60) Port P6 is an 8-bit input/output port which can be configured as an input or an output in 1-bit unit. Port P6 is also used as an analog input, key-on wakeup input and external interrupt input. Input/output mode is specified by the P6 control register (P6CR1) and input control register (P6CR2). When used as an output port, the corresponding bit of P6CR1 should be set to "1". When used as an input port, key-on wakeup input or an external interrupt input, the corresponding bit of P6CR1 should be cleared to "0", and then, the corresponding bit of P6CR2 should be set to "1". When used as an analog input, the corresponding bit of P6CR1 should be cleared to "0", and then, the corresponding bit of P6CR2 should be cleared to "0". During reset, the output latch (P6DR) and P6CR1 are initialized to "0", P6CR2 is initialized to "1". When the bit of P6CR1 and P6CR2 is "0", the corresponding bit data by read instruction is always "0". When the bit of P6CR1 is "0" and that of P6CR2 is "1", the corresponding bit data by read instruction is a terminal input data. When the bit of P6CR1 is "1", the corresponding bit data by read instruction is the value of P6DR. Table 5-7 Register Programming for Multi-function Ports Programmed Value Function P6DR Port input external interrupt input or key-on wakeup input Analog input Port "0" output Port "1" output * * "0" "1" P6CR1 "0" "0" "1" "1" P6CR2 "1" "0" * * Note: Asterisk (*) indicates "1" or "0" either of which can be selected. Table 5-8 Values Read from P6DR and Register Programming Conditions Values Read from P6DR P6CR1 "0" "0" "1" "1" P6CR2 "0" "1" "0" Output latch contents "0" Terminal input data Page 62 TMP86CM27FG P6CR2i P6CR2i input P6CR1i P6CR1i input Control input Data input (P6DRi) D Q D Q Data output (P6DRi) STOP OUTTEN Analog input AINDS SAIN D Q P6i a) P67, P63, P62, P61 Key-on wakeup STOPk P6CR2j P6CR2j input P6CR1j P6CR1j input Data input (P6DRj) D Q D Q Data output (P6DRj) STOP OUTTEN Analog input AINDS SAIN D Q P6i b) P66, P65, P64, P60 Note 1: i = 1 to 3 and 7, j = 4 to 6 and 0, k = 2 to 5 Note 2: STOP is bit7 in SYSCR1. Note 3: SAIN is AD input select signal. Note 4: STOPk is input select signal in a key-on wakeup. Figure 5-8 Port 6 Note 1: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. Note 2: When used as an analog inport, be sure to clear the corresponding bit of P6CR2 to disable the port input. Note 3: Do not set the output mode (P6CR1 = "1") for the pin used as an analog input pin. Note 4: Pins not used for analog input can be used as I/O ports. During AD conversion, output instructions should not be executed to keep a precision. In addition, a variable signal should not be input to a port adjacent to the analog input during AD conversion. Page 63 5. I/O Ports 5.7 Port P6 (P67 to P60) TMP86CM27FG P6DR (0006H) R/W 7 P67 AIN7 6 P66 AIN6 STOP4 5 P65 AIN5 STOP3 4 P64 AIN4 STOP2 3 P63 AIN3 INT0 2 P62 AIN2 1 P61 AIN1 0 P60 AIN0 STOP5 (Initial value: 0000 0000) P6CR1 (0014H) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P6CR1 I/O control for port P6 (Specified for each bit) 0: Input mode 1: Output mode R/W P6CR2 (0015H) 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) P6CR2 P6 port input control (Specified for each bit) 0: Analog input 1: Port input, external interrupt input or key-on wakeup input R/W Page 64 TMP86CM27FG 5.8 Port P7 (P77 to P70) Port P7 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P7 is also used as a segment output of LCD. When used as an input port, the corresponding bit of P7LCR should be cleared to "0", and the respective P7DR bit should be set to "1". When used as an output port, the respective P7LCR bit should be cleared to "0". When used as a segment pins of LCD, the respective bit of P7LCR should be set to "1". During reset, the output latch (P7DR) are initialized to "1", and P7LCR are initialized to "0". P7 port output latch (P7DR) and P7 port terminal input (P7PRD) are located on their respective address. When read the output latch data, the P7DR should be read and when read the terminal input data, the P7PRD register should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is read. Table 5-9 Register Programming for Multi-function Ports Programmed Value Function P7DR Port input Port "0" output LCD segment outputt "1" "0" * P7LCR "0" "0" "1" Note: Asterisk (*) indicates "1" or "0" either of which can be selected. STOP OUTEN P7LCRi P7CRi input D Q Terminal input (P7PRD) Output latch data (P7DR) Data output (P7DR) D Q P7i Output latch LCD data output Note: i = 7 to 0 Figure 5-9 Port 7 Page 65 5. I/O Ports 5.8 Port P7 (P77 to P70) TMP86CM27FG P7DR (0007H) R/W 7 P77 SEG8 6 P76 SEG9 5 P75 SEG10 4 P74 SEG11 3 P73 SEG12 2 P72 SEG13 1 P71 SEG14 0 P70 SEG15 (Initial value: 1111 1111) P7LCR (0FAFH) (Initial value: 0000 0000) P7LCR Port P7/segment output control (Set for each bit individually) 0: P7 input/output port 1: Segment output R/W P7PRD (0024H) Read only P77 P76 P75 P74 P73 P72 P71 P70 (Initial value: 0000 0000) Page 66 TMP86CM27FG 6. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 6.1 Time Base Timer 6.1.1 Configuration MPX fc/223 or fs/215 fc/221 or fs/213 fc/216 or fs/28 fc/214 or fs/26 fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/29 or fs/2 Source clock Falling edge detector IDLE0, SLEEP0 release request INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 6-1 Time Base Timer configuration 6.1.2 Control Time Base Timer is controled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (0036H) (DVOEN) 6 (DVOCK) 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 fc/223 fc/221 fc/216 fc/2 14 DV7CK = 1 fs/215 fs/213 fs/28 fs/2 6 SLOW1/2 SLEEP1/2 Mode fs/215 fs/213 - - - - - - R/W TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 fc/213 fc/2 12 fs/25 fs/2 4 fc/211 fc/2 9 fs/23 fs/2 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Page 67 6. Time Base Timer (TBT) 6.1 Time Base Timer TMP86CM27FG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously. Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET (EIRL) . 7 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 ; TBTEN 1 ; IMF 0 Table 6-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 NORMAL1/2, IDLE1/2 Mode DV7CK = 1 1 4 128 512 1024 2048 4096 16384 1 4 - - - - - - SLOW1/2, SLEEP1/2 Mode 6.1.3 Function An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 6-2 ). Source clock TBTCR INTTBT Interrupt period Enable TBT Figure 6-2 Time Base Timer Interrupt Page 68 TMP86CM27FG 6.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 6.2.1 Configuration Output latch Data output D Q DVO pin fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/210 or fs/22 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 6-3 Divider Output 6.2.2 Control The Divider Output is controlled by the Time Base Timer Control Register. Time Base Timer Control Register 7 TBTCR (0036H) DVOEN 6 DVOCK 5 4 (DV7CK) 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 fs/25 fs/24 fs/23 fs/22 SLOW1/2 SLEEP1/2 Mode fs/25 fs/24 fs/23 fs/22 R/W DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/213 fc/212 fc/211 fc/210 R/W Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Page 69 6. Time Base Timer (TBT) 6.2 Divider Output (DVO) TMP86CM27FG Example :1.95 kHz pulse output (fc = 16.0 MHz) LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 6-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k DV7CK = 1 1.024 k 2.048 k 4.096 k 8.192 k SLOW1/2, SLEEP1/2 Mode 1.024 k 2.048 k 4.096 k 8.192 k Page 70 TMP86CM27FG 7. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 Watchdog Timer Configuration Reset release fc/2 or fs/2 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29 23 15 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 7-1 Watchdog Timer Configuration Page 71 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86CM27FG 7.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 7.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 72 TMP86CM27FG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 (ATAS) 4 (ATOUT) 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 217/fs 215/fs 213/fs 211/fs SLOW1/2 mode 217/fs 215fs 213fs 211/fs Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTOUT to "0", the program cannot set it to "1". Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "1.2.3 Watchdog Timer Disable". Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 7.2.2 Watchdog Timer Enable Setting WDTCR1 Page 73 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86CM27FG 7.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary coutner : WDTEN 0, WDTCR2 Disable code Table 7-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time[s] WDTT DV7CK = 0 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m NORMAL1/2 mode DV7CK = 1 4 1 250 m 62.5 m SLOW mode 4 1 250 m 62.5 m 7.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Example :Setting watchdog timer interrupt LD LD SP, 043FH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 Page 74 TMP86CM27FG 7.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs Write 4EH to WDTCR2 Figure 7-2 Watchdog Timer Interrupt Page 75 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86CM27FG 7.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 ATAS 4 ATOUT 3 (WDTEN) 2 (WDTT) 1 0 (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area Select opertion at address trap 0: Generate no address trap 1: Generate address traps (After setting ATAS to "1", writing the control code D2H to WDTCR2 is reguired) 0: Interrupt request 1: Reset request Write only ATOUT Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only 7.3.1 Selection of Address Trap in Internal RAM (ATAS) WDTCR1 7.3.2 Selection of Operation at Address Trap (ATOUT) When an address trap is generated, either the interrupt request or the reset request can be selected by WDTCR1 7.3.3 Address Trap Interrupt (INTATRAP) While WDTCR1 Page 76 TMP86CM27FG 7.3.4 Address Trap Reset While WDTCR1 Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 77 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86CM27FG Page 78 TMP86CM27FG 8. 10-Bit Timer/Counter (TC7) 8.1 Configuration CSIDIS TC7CR3 TC7ST EMGF fc fc/2 fc/22 fc/23 PPG2INI PPG1INI A B C D S CSTC STM CNTBF INTTC7T interrupt request Y 10-bit up counter Start/ clear TGRAM TC7CK TC7CR1 NCRSEL TRGSEL Edge detection CSIDIS TC7CAPA Capture control TC7CAPB TC7 pin Noise canceller INTTC7P interrupt request PPG1 Comparator PPG output control TC7OUT PPG1OE/ PPG1INI/ PPG2OE PPG2INI PPG2 Compare register A Compare register B Compare register C Compare register D Compare register E Transfer control TC7DRA TC7DRB TC7DRC TC7DRD TC7DRE EMGF Emergency stop EMG pin Emergency output stop control EMGIE CSTC EMGR INTEMG interrupt request PPG2OE PPG1OE TC7CR2 TC7OUT Figure 8-1 10-Bit Timer/Counter 7 8.2 Control Timer/counter 7 is controlled by timer/counter control register 1 (TC7CR1), timer/counter control register 2 (TC7CR2), timer/counter control register 3 (TC7CR3), 10-bit dead time 1 setup register (TC7DRA), pulse width 1 setup register (TC7DRB), period setup register (TC7DRC), dead time 2 setup register (TC7DRD), pulse width 2 setup register (TC7DRE), and two capture value registers (TC7CAPA and TC7CAPB). Timer/Counter 7 Control Register 1 TC7CR1 (0029H) 7 TRGAM 6 TRGSEL 5 PPG2INI 4 PPG1INI 3 NCRSEL 2 1 TC7CK 0 (Initial value: 0000 0000) Page 79 8. 10-Bit Timer/Counter (TC7) 8.2 Control TMP86CM27FG TC7CK Select a source clock (Supplied to the up counter). 00: fc 01: fc/2 10 fc/22 [Hz] [Hz] [Hz] 11: fc/23 [Hz] Select the duration of noise elimination for TC7 input (after passing through the flip-flop). Specify the initial value of PPG1 output. Specify the initial value of PPG2 output. 00: Eliminate pulses shorter than 16/fc [s] as noise. 01: Eliminate pulses shorter than 8/fc [s] as noise. 10: Eliminate pulses shorter than 4/fc [s] as noise. 11: Do not eliminate noise. (Note) 0: Low (Positive logic) 1: High (Negative logic) 0: Low (Positive logic) 1: High (Negative logic) NCRSEL PPG1INI Select positive or negative logic. R/W PPG2INI 0: Start on trigger falling edge. TRGSEL Select a trigger start edge. 1: Start on trigger rising edge. 0: Always accept trigger edges. 1: Do not accept trigger edges during active output. TRGAM Trigger edge acceptance mode Note: Due to the circuit configuration, a pulse shorter than 1/fc may be eliminated as noise or accepted as a trigger. Timer/Counter 7 Control Register 2 TC7CR2 (002AH) 7 EMGR 6 EMGIE 5 PPG2OE 4 PPG1OE 3 CSTC 2 1 TC7OUT 0 (Initial value: 0000 0000) TC7OUT Select an output waveform mode. 00: PPG1/PPG2 independent output 01: - 10: Output with variable duty ratio 11: Output with 50% duty ratio 00: Command start and capture mode 01: Command start and trigger start mode. 10: Trigger start mode 11: 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable input. 1: Enable input. 0: 1: Cancel the emergency output stop state. (Upon canceling the state, this bit is automatically cleared to 0.) R/W CSTC Select a count start mode. PPG1OE PPG2OE EMGIE Enable/disable PPG1 output. Enable/disable PPG2 output. Enable/disable input on the EMG pin. EMGR Cancel the emergency output stop state. Timer/Counter 7 Control Register 3 TC7CR3 (002BH) 7 6 5 EMGF 4 CNTBF 3 CSIDIS 2 STM 1 0 TC7ST (Initial value: **00 0000) Page 80 TMP86CM27FG TC7ST Start/stop the timer. 0: Stop 1: Start TC7ST = 0 00: Immediately stop and clear the counter with the output initialized. TC7ST = 1 Continuous output Continuous output One-time output - STM Select the state when stopped. Select continuous or one-time output. 01: Immediately stop and clear the counter with the output maintained. 10: Stop the counter after completing output in the current period. 11: - R/W CSIDIS Disable the first interrupt at upon a command start. 0: Allow a periodic interrupt (INTTC7P) to occur in the first period upon a command start. 1: Do not allow a periodic interrupt (INTTC7P) to occur in the first period upon a command start. 0: Counting stopped 1: Counting in progress 0: Operating normally 1: Output stopped in emergency CNTBF EMGF Counting status flag Emergency output stop flag Read only Note 1: The TC7CR1 and TC7CR2 registers should not be rewritten after a timer start (when TC7ST, bit0 of the TC7CR3, is set to 1). Note 2: Before attempting to modify the TC7CR1 or TC7CR2, clear TC7ST and then check that CNTBF = 0 to determine that the timer is stopped. Note 3: The TC7ST bit only causes the timer to start or stop; it does not indicate the current operating state of the counter. Its value does not change automatically when counting starts or stops Note 4: In command start and capture mode or command start and trigger start mode, writing 1 to TC7ST causes the timer to restart immediately. It means that rewriting any bit other than TC7ST in the TC7CR3 after a command start causes the rewriting of TC7ST, resulting in the timer being restarted (PPG output is started from the initial state). When TC7ST is set to 1, rewriting the TC7CR3 (Using a bit manipulation or LD instruction) clears the counter and restarts the timer. Note 5: TC7CR2 Dead Time 1 Setup Register 15 TC7DRA (0009H, 0008H) Read/Write (Initial value: **** **00 0000 0000) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC7DRAH (0009H) TC7DRAL (0008H) Pulse Width 1 Setup Register 15 TC7DRB (000BH, 000AH) Read/Write (Initial value: **** **00 0000 0000) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC7DRBH (000BH) TC7DRBL (000AH) Period Setup Register 15 TC7DRC (000DH, 000CH) Read/Write (Initial value: **** **00 0000 0000) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC7DRCH (000DH) TC7DRCL (000CH) Page 81 8. 10-Bit Timer/Counter (TC7) 8.2 Control TMP86CM27FG Dead Time 2 Setup Register 15 TC7DRD (0FB1H, 0FB0H) Read/Write (Initial value: **** **00 0000 0000) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC7DRDH (0FB1H) TC7DRDL (0FB0H) Pulse Width 2 Setup Register 15 TC7DRE (0FB3H, 0FB2H) Read/Write (Initial value: **** **00 0000 0000) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC7DREH (0FB3H) TC7DREL (0FB2H) Note 1: Data registers TC7DRA to TC7DRE have double-stage configuration, consisting of a data register that stores data written by an instruction and a compare register to be compared with the counter. Note 2: When writing data to data registers TC7DRA to TC7DRE, first write the lower byte and then the upper byte. Note 3: Unused bits (Bits 10 to 15) in the upper bytes of data registers TC7DRA to TC7DRE are not assigned specific register functions. These bits are always read as 0 even when a 1 is written. Note 4: Values read from data registers TC7DRA to TC7DRE may differ from the actual PPG output waveforms due to their double-stage configuration. Note 5: Data registers are not updated by merely modifying the output mode with TC7CR2 Rising-edge Capture Value Register 15 TC7CAPA (0FB5H, 0FB4H) Read only (Initial value: 0000 00** **** ****) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC7CAPAH (0FB5H) TC7CAPAL (0FB4H) Falling-edge Capture Value Register 15 TC7CAPB (0FB7H, 0FB6H) Read only (Initial value: 0000 00** **** ****) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC7CAPBH (0FB7H) TC7CAPBL (0FB6H) Note 1: Capture registers (TC7CAPA and TC7CAPB) must be read in the following order: Lower byte of the TC7CAPA, upper byte of the TC7CAPA, lower byte of the TC7CAPB, upper byte of the TC7CAPB. Note 2: The next captured data is not updated by reading the TC7CAPA only. The TC7CAPB must also be read. Note 3: It is possible to read the TC7CAPB only. Read the lower byte first. Note 4: If a capture edge is not detected within a period, the previous capture value is maintained in the next period. Note 5: If more than one capture edge is detected within a period, the capture value for the edge detected last is valid in the next period. Note 6: Bits 10 to 15 of the TC7CAPA and TC7CAPB are always read as 0. Page 82 TMP86CM27FG 8.3 Configuring Control and Data Registers Configure control and data registers in the following order: 1. Configure mode settings: TC7CR1, TC7CR2 2. Configure data registers (Dead time, pulse width): TC7DRA, TC7DRB, TC7DRD, TC7DRE (only those required for selected mode) 3. Configure data registers (Period): TC7DRC 4. Configure timer start/stop:TC7CR3 * Data registers have double-stage configuration, consisting of a data register that stores data written by an instruction and a compare register to be compared with the counter. * Data stored in a data register is processed according to the output mode specified in the TC7OUT, transferred to the compare register, and then used for comparison with the up counter. * Data registers required for the specified output mode are used for data register processing and transfer to the compare register. Ensure that the output mode is specified in the TC7OUT (Bits 0 and 1 of the TC7CR2) before configuring data registers. * Writing data to the upper byte of the TC7DRC causes a data transfer request to be issued for data in data registers TC7DRA to TC7DRE. If a counter match or clear occurs while that request is valid, the data is transferred to the compare register and becomes valid for comparison. * If a data register is written more than once within a period, the data in the data register that was set when the upper byte of the TC7DRC was written is valid as data for the next period. The data in the data register written last in the first period will be valid for the period that follows the next period. Execute write instruction. Execute write instruction. Execute write instruction. TC7DRA TC7DRB TC7DRC A1 B1 C1 A2 B2 C2 A3 B3 C3 Valid in next period Period (1) Period (2) Period (3) Previous data is maintained if data is not rewritten within the period. Period (4) Execute write instruction. Execute more than one data write instruction. Execute write instruction. No data write Execute write instruction. TC7DRA TC7DRB TC7DRC A1 B1 C1 A2 C2 C3 B2 C4 A3 C5 A4 C6 A5 C7 A6 B3 C8 A7 B4 C9 Data valid in each period A1 B1 C1 A2 B1 C2 A3 B2 C5 A5 B2 C7 A6 B3 C8 Period (5) Period (1) If data is rewritten more than once within a period, the data written first is valid in the next period. Period (2) If data is rewritten more than once within a period, the data written last is valid in the period following the next period. Period (3) Period (4) Figure 8-2 Example Configuration of Control/data Registers (1) Page 83 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG More than one data write No data write More than one data write TC7DRA TC7DRB TC7DRC A1 B1 C1 A2 B2 C2 A3 B3 C3 A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C3 Data valid in each period a1 b1 c1 A1 B1 C1 A3 B3 C3 A1 B1 C1 A3 B3 C3 A4 B4 C3 Period (6) Period (1) Period (2) Period (3) Period (4) Period (5) If TC7DRC is written in the next period Figure 8-3 Example Configuration of Control/data Registers (2) 8.4 Features 8.4.1 Programmable pulse generator output (PPG output) The PPG1 and PPG2 pins provide PPG outputs. The output waveform mode for PPG outputs is specified with TC7CR2 8.4.1.1 50% duty mode (1) Description With a period specified in the TC7DRC, the PPG1 and PPG2 pins provide waveforms having a pulse width (Active duration) that equals a half the period. The PPG1 output is active at the beginning of a period and becomes inactive at half the period. The PPG2 output is inactive at the beginning of a period, becomes active at half the period, and remains active until the end of the period. If a dead time is specified in the TC7DRA, the pulse width (Active duration) is shortened by the dead time. (2) Register settings TC7OUT = "11", TC7DRA = "dead time", TC7DRC = "period" (3) Valid range for data register values (a) Period: 002H TC7DRC 400H (Writing 400H to TC7DRC results in 000H being read from it.) Page 84 TMP86CM27FG When the value set in the TC7DRC is an odd number, the PPG2 pulse width is one count longer than the PPG1 pulse width. (b) Dead time TC7DRA: 000H TC7DRA < TC7DRC/2 To specify no dead time, set the TC7DRA to 000H. Source clock Counter S, 0 1 M S/2 S/2+1 S/2+M S, 0 1 2 3 Dead time M M' Period S M: Dead time S PPG1 output Active duration M: Dead time S: Period PPG2 output Active duration INTTC7T INTTC7P Dead time (TC7DRA) Dead time (TC7DRA) Pulse width (TC7DRC/2) Pulse width (TC7DRC/2) Period (TC7DRC) Figure 8-4 Example operation in 50% duty mode: Command and capture start, positive logic, continuous output 8.4.1.2 Variable duty mode (1) Description With a period specified in the TC7DRC and a pulse width in the TC7DRB, the PPG1 pin provides a waveform having the specified pulse width while the PPG2 pin provides a waveform having a pulse width that equals (TC7DRC - TC7DRB). The PPG1 output is active at the beginning of a period, remains active during the pulse width specified in the TC7DRB, after which it is inactive until the end of the period. The PPG2 output is inactive at the beginning of a period, remains inactive during the pulse width specified in the TC7DRB, after which it is active until the end of the period, that is, during the pulse width of (TC7DRC - TC7DRB). If a dead time is specified in the TC7DRA, the pulse width (Active duration) is shortened by the dead time. (2) Register settings TC7OUT = "10", TC7DRA = "dead time", TC7DRB = "pulse width", TC7DRC = "period" Page 85 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG (3) Valid range for data register values (a) Period: 002H TC7DRB + TC7DRA < TC7DRC 400H (Writing 400H to TC7DRC results in 000H being read from it.) (b) Pulse width: 001H TC7DRB < TC7DRC (c) Dead time: 000H TC7DRA < TC7DRB, 000H TC7DRA < (TC7DRC - TC7DRB) (To specify no dead time, set the TC7DRA to 000H.) Source clock Counter S, 0 1 M N N+1 N+M S, 0 1 2 3 Dead time M M' Pulse width N N' Period S M: Dead time Active duration N: Pulse width S: Period M: Dead time S PPG1 output PPG2 output Active duration INTTC7T INTTC7P Dead time (TC7DRA) Pulse width (TC7DRB) Dead time (TC7DRA) Pulse width (TC7DRC - TC7DRB) Period (TC7DRC) Figure 8-5 Example Operation in Variable Duty Mode: Command and Capture Start, Positive Logic, Continuous Output 8.4.1.3 PPG1/PPG2 independent mode (1) Description For the PPG1 output, specify the dead time in the TC7DRA and pulse width in the TC7DRB. For the PPG2 output, specify the dead time in the TC7DRD and pulse width in the TC7DRE. With a common period specified in the TC7DRC, the PPG1 and PPG2 pins provide waveforms having the specified pulse widths. Page 86 TMP86CM27FG The PPG1 output is active at the beginning of a period, remains active during the pulse width specified in the TC7DRB, after which it is inactive until the end of the period. The PPG2 output is active at the beginning of a period, remains active during the pulse width specified in the TC7DRE, after which it is inactive until the end of the period. If a dead time is specified in the TC7DRA for the PPG1 output or in the TC7DRD for the PPG2 output, the pulse width (Active duration) is shortened by the dead time. (2) Register settings TC7OUT = "00", TC7DRC = "period" TC7DRA = "PPG1 dead time", TC7DRB = "PPG1 pulse width" TC7DRD = "PPG2 dead time", TC7DRE = "PPG2 pulse width" (3) Valid range for data register values (a) Period: 002H TC7DRC 400H (Writing 400H to TC7DRC results in 000H being read from it.) (b) Pulse width: 001H TC7DRB 400H (Writing 400H to TC7DRB results in 000H being read from it.) 001H TC7DRE 400H (Writing 400H to TC7DRE results in 000H being read from it.) (c) Dead time: 000H TC7DRA 3FFH, where TC7DRA < TC7DRB TC7DRC 000H TC7DRD 3FFH, where TC7DRD < TC7DRE TC7DRC (To specify no dead time, write 000H.) * Settings for a duty ratio of 0% 002H TC7DRC TC7DRA 3FFH (PPG1 output) 002H TC7DRC TC7DRD 3FFH (PPG2 output) * Settings for a duty ratio greater than 0%, up to 100% 000H TC7DRA < TC7DRB TC7DRC 400H (PPG1 output) 000H TC7DRD < TC7DRE TC7DRC 400H (PPG2 output) Period Period 0% duty 100% duty Page 87 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG Source clock Counter 0 1 M T N U S, 0 1 2 3 Dead time M M' Pulse width N N' Period S S Dead time T T' Pulse width U M: Dead time Active duration N: Pulse width U' PPG1 output PPG2 output T: Dead time U: Pulse width Active duration INTTC7T S: Period INTTC7P PPG1 dead time (TC7DRA) PPG1 pulse width (TC7DRB) PPG2 dead time (TC7DRD) PPG2 pulse width (TC7DRE) Period (TC7DRC) Figure 8-6 Example Operation in PPG1/PPG2 Independent Mode: Command and Capture Start, Positive Logic, Continuous Output 8.4.2 Starting a count A count can be started by using a command or TC7 pin input. 8.4.2.1 Command start and capture mode (1) Description Writing a 1 to TC7ST causes the current count to be cleared and the counter to start counting. Once the count has reached a specified period, the counter is cleared. The counter subsequently restarts counting if STM specifies continuous mode; it stops counting if STM specifies one-time mode. Writing a 1 to TC7ST before the count reaches a period causes the counter to be cleared, after which it operates as specified with STM. The count values at the rising and falling edges on the TC7 pin can be stored in capture registers (Details for the capture are given in a separate section). Page 88 TMP86CM27FG (2) Register settings CSTC = "00": Command start and capture mode STM: Continuous/one-time output TC7ST = "1": Starts counting PPG1 Count start (Command) Count cleared Start Count cleared Start TC7ST = 1 Count cleared Restart PPG output with a period specified with TC7DRC PPG output with a period specified with TC7DRC PPG output with a period specified with TC7DRC Figure 8-7 Example Operation in Command Start and Capture Mode 8.4.2.2 Command start and trigger start mode (1) Description Writing a 1 to TC7ST causes the current count to be cleared and the counter to start counting. The operation is the same as that in command start and capture mode if there is no trigger input on the TC7 pin. If an edge specified with the start edge selection field (TRGSEL) appears on the TC7 pin, however, the timer starts counting. The counter is cleared and stopped while the TC7 pin is driven to the specified clear/stop level. If the TC7 pin is at the clear/stop level when a count start command is issued (1 is written to TC7ST), counting does not start (INTTC7P does not occur) until a trigger start edge appears, causing INTTC7T to occur (A trigger input takes precedence over a command start). Note: For more information on the acceptance of a trigger, see 8.4.2.5 "Trigger start/stop acceptance mode". (2) Register settings CSTC = "01": Command start and trigger start mode STM: Continuous/one-time output TC7ST = "1": Starts counting TRGSEL: Trigger selection Count stopped Period (TC7DRC) TC7 input (Signal after noise elimination) PPG1 Count start (Command) PPG output with a period When TRGSEL = 0 (Start on falling edge) specified with TC7DRC if there is no trigger Count cleared Start Count cleared Count start Count starts with a trigger (Falling edge). Count stops with a trigger (High level). Figure 8-8 Example Operation in Command Start and Trigger Start Mode Page 89 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG 8.4.2.3 Trigger start mode (1) Description If an edge specified with the start edge selection field (TRGSEL) appears on the TC7 pin, the timer starts counting. The counter is cleared and stopped while the TC7 pin is driven to the specified clear/ stop level. In trigger start mode, writing a 1 to TC7ST is ignored and does not initialize the PPG output. Note: For more information on the acceptance of a trigger, see 8.4.2.5 "Trigger start/stop acceptance mode". (2) Register settings CSTC = "10": Trigger start mode STM: Continuous/one-time output TC7ST = "1": Starts waiting for a trigger on the TC7 pin TRGSEL: Trigger selection TC7 input (Signal after noise elimination) PPG1 output (Example) Command set After a command is set, counting does not start until a specified trigger appears. Count start Count stopped Count stopped Count cleared Count start Count cleared TC7 input (Signal after noise elimination) PPG1 output (Example) Command set After a command is set, counting does not start until a specified trigger appears. Count start Count stopped Count cleared Count start Figure 8-9 Example Operation in Trigger Start Mode 8.4.2.4 Trigger capture mode (CSTC = 00) (1) Description When counting starts in command start and capture mode, the count values at the rising and falling edges of the TC7 pin input are captured and stored in capture registers TC7CAPA and TC7CAPB, respectively. Page 90 TMP86CM27FG The captured data is first stored in the capture buffer. At the end of the period, the data is transferred from the capture buffer to the capture register. If a trigger input does not appear within a period, the data captured in the previous period remains in the capture buffer and is transferred to the capture register at the end of the period. If more than one trigger edge is detected within a period, the data captured last is written to the capture register. Captured data must be read in the following order: Lower byte of capture register A (TC7CAPAL), upper byte of capture register A (TC7CAPAH), lower byte of capture register B (TC7CAPBL), and upper byte of capture register B (TC7CAPBH). Note that reading only the rising-edge captured data (TC7CAPA) does not update the next captured data. The falling-edge captured data (TC7CAPB) must also be read. An attempt to read a captured value from a register other than the upper byte of the TC7CAPB causes the capture registers to enter protected state, in which captured data cannot be updated. Reading a value from the upper byte of the TC7CAPB cancels that state, re-enabling the updating of captured data (The TC7CAPA and TC7CAPB are read as a single set of operation). Note that the protected state may be still effective immediately after the counter starts. Ensure that a dummy read of capture registers is performed in the first period to cancel the protected state. The capture feature of the TC7 assumes that a capture trigger (Rising or falling edge) appears within a period. Captured data is updated (An edge is detected) only when the timer is operating (TC7ST = 1). If a timer stop command (TC7ST = 0) is written within a period, captured data will be undefined. Captured data is not updated after a one-time stop command is written. In one-time stop mode, no trigger is accepted after a STOP command is given. (2) Register settings CSTC = "00": Command start and capture mode STM: Continuous/one-time output TC7ST = "1": Starts counting Page 91 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG 1 period Rising edge TC7 input (Signal after noise elimination) Falling edge Rising edge 1 period Falling edge a b c d a Capture buffers c b d x Capture registers a c y b d Captured values read (Data read skipped) Captured values read (a and b read) Captured values read (c and d read) 1 period TC7 input (Signal after noise elimination) 1 period 1 period 1 period a b c d a1 b1 c1 a2 c2 a Capture buffers c a1 c1 c2 b d b1 a2 x Capture registers c a1 c1 c2 y d d Started reading other than upper CAPB in this period b1 a2 Captured values read (Data read skipped) Captured values read (c and d read) Captured values read (a1 and d read) Figure 8-10 Example Operation in Trigger Capture Mode 8.4.2.5 Trigger start/stop acceptance mode (1) Selecting an input signal logic for the TC7 pin (Trigger input) The logic for an input trigger signal on the TC7 pin can be specified using TC7CR1 Page 92 TMP86CM27FG TRGSEL = 0 Counter operating Counter stopped Counter operating TRGSEL = 1 Counter operating Counter stopped Counter operating TC7 pin input TC7 pin input Count started Count cleared Count started Count started Count cleared Count started Figure 8-11 Trigger Input Signal When TRGSEL is set to 0 to select a falling-edge trigger, a falling edge detected on the TC7 pin causes the counter to start counting and a high level on the TC7 pin causes the counter to be cleared and the PPG output to be initialized. The counter is stopped while the TC7 pin input is high. When TRGSEL is set to 1 to select a rising-edge trigger, a rising edge detected on the TC7 pin causes the counter to start counting and a low level on the TC7 pin causes the counter to be cleared and the PPG output to be initialized. The counter is stopped while the TC7 pin input is low. In one-time stop mode, the counter accepts a stop trigger but does not accept a start trigger (when a stop trigger is accepted within a period, the output is immediately initialized and the counter is stopped). Counter stopped TC7 pin input PPG output Counting stop mode with the outputs at the end of the period Initial value One-time mode Count cleared All triggers (Start and stop) are ignored when the timer is stopped (TC7ST = 0). (2) Specifying whether triggers are always accepted or ignored when PPG outputs are active The TC7CR1 Page 93 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG TC7 pin input PPG1 output (Positive logic) PPG2 output (Positive logic) INTTC7T INTTC7P Counter operating Count started Counter stopped Count cleared Count started Counter operating Counter stopped Count cleared Counter Counter operating stopped Count cleared Count started Counter operating End of a period Count started Figure 8-12 Start and Clear/stop Triggers on the TC7 Pin: Falling-edge Trigger (Counting stopped at high level), Triggers Always Accepted (3) Ignoring triggers when PPG outputs are active Setting TRGAM to 1 specifies that triggers are ignored when PPG outputs are active; trigger edges detected when PPG1 and PPG2 outputs are inactive are accepted and cause the counter to be cleared and stopped. If a trigger is detected when PPG1 and PPG2 outputs are active, the counter does not stop immediately but continues counting until the outputs become inactive. If the trigger signal level is a stop level when the outputs become inactive, the counter is cleared/stopped and waits for a next start trigger. If output is enabled for both PPG1 and PPG2, triggers are accepted only when both PPG1 and PPG2 outputs are inactive. Triggers not accepted TC7 pin input (Signal after noise elimination) IGBT1 (Positive logic) IGBT2 (Positive logic) INTTC7 INTTCR Counter operating Counter stopped Counter operating Counter stopped Counter operating A trigger detected when PPG1 and PPG2 are inactive causes the counter to stop or start. A trigger detected when PPG1 or PPG2 is active does not cause the counter to stop. A high level of the trigger input causes the counter to stop when PPG1 and PPG2 become inactive. A trigger detected when PPG1 or PPG2 is active does not cause the counter to stop or restart. Figure 8-13 Start Triggers on the TC7 Pin: Falling-edge Trigger (Counting stopped at high level), Triggers Ignored when PPG Outputs are Active Page 94 TMP86CM27FG 8.4.3 Configuring how the timer stops Setting TC7ST to 0 causes the timer to stop with the specified output state according to the setting of STM. 8.4.3.1 Counting stopped with the outputs initialized When STM is set to 00, the counter stops immediately with the PPG1 and PPG2 outputs initialized to the values specified with PPG1INI and PPG2INI. 8.4.3.2 Counting stopped with the outputs maintained When STM is set to 01, the counter stops immediately with the current PPG1 and PPG2 output states maintained. To restart the counter from the maintained state (STM = 01), set TC7ST to 1. The counter is restarted with the initial output values, specified with PPG1INI and PPG2INI. 8.4.3.3 Counting stopped with the outputs initialized at the end of the period When STM is set to 10, the counter continues counting until the end of the current period and then stops. If a stop trigger is detected before the end of the period, however, the counter stops immediately. TC7CR1 and TC7CR2 must not be rewritten before the counter stops completely. The CNTBF flag (TC7CR3 8.4.4 One-time/continuous output mode One-time output mode Starting the timer (TC7ST = 1) with STM set to 10 specifies one-time output mode. In this mode, the timer stops counting at the end of a period. For a trigger start, the counter is stopped until a trigger is detected. A specified trigger restarts counting and the counter stops at the end of the period or when a stop trigger is detected, after which it waits for a trigger again. For a command start, the counter is stopped until TC7ST is reset to 1. TC7CR1 and TC7CR2 must not be rewritten before the counter stops completely. The CNTBF flag (TC7CR3 8.4.4.1 8.4.4.2 Continuous output mode Starting the timer (TC7ST = 1) with STM set to 00 or 01 specifies continuous output mode. In this mode, the timer outputs specified waveforms continuously. Page 95 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG PPG1 (Positive logic) PPG1INI = 0 PPG2 (Negative logic) PPG1INI = 1 The counter is forcibly stopped and cleared, with the outputs initialized. STOP command TC7ST = 0 Output enabled Count started PPG1E/PPG2E = 1 TC7ST = 1 STM = 00 Figure 8-14 Immediately Stopping and Clearing the Counter with the Outputs Initialized (STM = 00) PPG1 (Positive logic) PPG1INI = 0 PPG2 (Negative logic) PPG1INI = 1 The counter is forcibly stopped and cleared, with the outputs maintained. Output enabled Count started PPG1E/PPG2E = 1 TC7ST = 1 STM = 01 STOP command TC7ST = 0 Figure 8-15 Immediately Stopping and Clearing the Counter with the Outputs Maintained (STM = 01) 1 period PPG1 (Positive logic) PPG1INI = 0 PPG2 (Negative logic) PPG1INI = 1 1 period After a stop command is executed, the counter continues counting until the end of the period. It stops at the end of the period. STOP command Count TC7ST = 0 stopped STM = 10 Output enabled Count started PPG1E/PPG2E = 1 TC7ST = 1 STM = 00 or 01 Figure 8-16 Stopping the Counter at the End of the Period (STM = 10) 1 period PPG1 (Positive logic) PPG1INI = 0 PPG2 (Negative logic) PPG1INI = 1 The counter stops at the end of the period and then waits for a command start or a start trigger. Output enabled PPG1E/PPG2E = 1 Count started TC7ST = 1 STM = 10 Count stopped at the end of the period Figure 8-17 Stopping the Counter at the End of the Period (STM = 10): TC7ST = 1, One-time Output Mode Page 96 TMP86CM27FG 8.4.5 PPG output control (Initial value/output logic, enabling/disabling output) Specifying initial values and output logic for PPG outputs The PPG1INI and PPG2INI bits (TC7CR1 8.4.5.1 8.4.5.2 Enabling or disabling PPG outputs The PPG1OE and PPG2OE bits (TC7CR2 8.4.5.3 Using the TC7 as a normal timer/counter The TC7 can be used as a normal timer/counter when PPG outputs are disabled using PPG1E and PPG2E. In that case, use an INTTC7P interrupt, which occurs upon a match with the value specified in the data register (TC7DRC). To start the counter, use start control (TC7S) in command start and capture mode. Start Source clock Counter 0 1 2 3 4 N/0 1 2 3 4 5 6 7 TC7DRC n Match detected INTTC7P Figure 8-18 Using the TC7 as a Normal Timer/Counter 8.4.6 Eliminating noise from the TC7 pin input A digital noise canceller eliminates noise from the input signal on the TC7 pin. The digital noise canceller uses a sampling clock of fc/4, fc/2 or fc, as specified with NCRSEL, and samples the signal five times. It accepts a level input which is continuous at least over the period of time required for five samplings. Any level input which does not continue over the period of time required for five samplings is canceled as noise. Page 97 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG Table 8-1 Noise Canceller Settings NCRSEL 00 01 10 11 Sampling Frequency (Number of Samplings) fc/4 (5) fc/2 (5) fc (5) (None) Pulse Width Always Assumed as Noise At 8 MHz 16/fc [s] 8/fc [s] 4/fc [s] None 2 [ms] 1 [ms] 0.5 [ms] - At 16 MHz 1 [ms] 500 [ns] 250 [ns] - 20/fc [s] 10/fc [s] 5/fc [s] (1/fc) Pulse Width Always Assumed as Signal At 8 MHz 2.5 [ms] 1.25 [ms] 0.625 [ms] At 16 MHz 1.25 [ms] 0.625 [ms] 0.3125 [ms] TC7 input F/F fc fc/4 fc/2 fc Noise canceller Sampling clock B A S Z Edge detection PPG output control circuit PPG output A B C Z NCRSEL = 11 NCRSEL 12345 fc 1 fc/2 1 fc/4 TC7 pin input (after passing through F/F) When NCRSEL = 00 Pulses of 16/fc or shorter are canceled. 12345 2 3 4 5 1 2 3 4 5 2 3 4 1 2 3 4 5 Pulses of 20/fc or longer are assumed as a signal. Pulses of 10/fc or longer are assumed as a signal. After noise elimination When NCRSEL = 01 Pulses of 8/fc or shorter are canceled. When NCRSEL = 10 Pulses of 4/fc or shorter are canceled. Pulses of 5/fc or longer are assumed as a signal. Figure 8-19 Noise Canceller Operation * When NCRSEL = 00, a TC7 input level after passing through the F/F is always canceled if its duration is 16/fc [s] or less and always assumed as a signal if its duration is 20/fc [s] or greater. After the input signal supplied on the TC7 pin passes through the F/F, there is a delay between 21/fc [s] and 24/fc [s] before the PPG outputs vary. * When NCRSEL = 01, a TC7 input level after passing through the F/F is always canceled if its duration is 8/fc [s] or less and always assumed as a signal if its duration is 10/fc [s] or greater. After the input signal supplied on the TC7 pin passes through the F/F, there is a delay between 13/fc [s] and 14/fc [s] before the PPG outputs vary. * When NCRSEL = 10, a TC7 input level after passing through the F/F is always canceled if its duration is 4/fc [s] or less and always assumed as a signal if its duration is 5/fc [s] or greater. After the input signal supplied on the TC7 pin passes through the F/F, there is a delay of 5/fc [s] before the PPG outputs vary. * When NCRSEL = 11, a pulse shorter than 1/fc may be assumed as a signal or canceled as noise in the first-stage F/F. Ensure that input signal pulses are longer than 1/fc. After the input signal supplied on the TC7 pin passes through the F/F, there is a delay of 4/fc [s] before the PPG outputs vary. Page 98 TMP86CM27FG Note 1: If the pin input level changes while the specified noise elimination threshold is being modified, the noise canceller may assume noise as a pulse or cancel a pulse as noise. Note 2: If noise occurs in synchronization with the internal sampling timing consecutively, it may be assumed as a signal. Note 3: The signal supplied on the TC7 pin requires 1/fc [s] or less to pass through the F/F. 8.4.7 Interrupts The TC7 supports three interrupt sources. 8.4.7.1 INTTC7T (Trigger start interrupt) A trigger interrupt (INTTC7T) occurs when the counter starts upon the detection of a trigger edge specified with TC7CR1 1 period TC7 trigger Cleared Count started Cleared Counter x 0 1 2 M-2 M-1 0 1 2 0 1 2 INTTC7T Cleared upon match TC7DRC INTTC7P PPG output Figure 8-20 Trigger Start Interrupt 8.4.7.2 INTTC7P (Period interrupt) A period interrupt (INTTC7P) occurs when the counter starts with a command and when the counter is cleared with the specified counter period (TC7DRC) reached, that is, at the end of a period. A match with the set period causes an interrupt even when the counter is stopped in emergency. Command stop Stop at the end of period Timer stopped Counter x 1 2 M-2 M-1 M, 0 1 2 M-2 M-1 M, 0 Command start INTTC7T Clear upon match TC7DRC INTTC7P PPG output CSIDIS specifies whether the first INTTC7P occurs. 1 period 1 period Figure 8-21 Period Interrupt Page 99 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG If a command start is specified (1 is written in TC7ST) when the TC7 pin is at a stop level, the counter does not start (INTTC7P does not occur); a subsequent trigger start edge causes the counter to start and INTTC7T to occur. 8.4.7.3 INTEMG (Emergency output stop interrupt) An emergency output stop interrupt (INTEMG) occurs when the emergency output stop circuit operates to stop PPG outputs in emergency. 8.4.8 Emergency PPG output stop feature Setting TC7CR2 Note:Ensure that a low level on the EMG pin continues for at least 4/fc [s]. The emergency PPG output stop feature may not operate normally with a low level shorter than 4/fc [s]. EMG interrupt (INTEMG) EMG pin Sampling circuit S R Q F/F EMGF (Status flag) Port output latch F/F F/F A B S Z PPG1OE PPG2OE EMGIE EMGR TC7 control register 2 PPG circuit output TC7ST STM TC7 control register 3 PPG1 PPG2 PPG1INI PPG1OE PPG2INI PPG2OE TC7 control register 1 Figure 8-22 EMG Pin 8.4.8.1 Enabling/disabling input on the EMG pin Setting TC7CR2 8.4.8.2 Monitoring the emergency PPG output stop state When the emergency PPG output stop feature activates, the TC7CR3 Page 100 TMP86CM27FG 8.4.8.3 EMG interrupt An EMG interrupt (INTEMG) occurs when an emergency PPG output stop input is accepted. To use an INTEMG interrupt for some processing, ensure that the interrupt is enabled beforehand. When the EMG pin is low with EMGIE set to 1 (EMG pin input enabled), an attempt to cancel the emergency PPG output stop state results in an interrupt being generated again, with the emergency PPG output stop state reestablished. An INTEMG interrupt occurs whenever a stop input is accepted when EMGIE = 1, regardless of whether the timer is operating. 8.4.8.4 Canceling the emergency PPG output stop state To cancel the emergency PPG output stop state, ensure that the input on the EMG pin is high, set TC7CR3 8.4.8.5 Restarting the timer after canceling the emergency PPG output stop state To restart the timer after canceling the emergency PPG output stop state, reconfigure the control registers (TC7CR1, TC7CR2, TC7CR3) before restarting the timer. The timer cannot restart in the emergency PPG output stop state. Monitor the emergency PPG output stop state and cancel the state before reconfiguring the control registers to restart the timer. Ensure that the control registers are reconfigured according to the appropriate procedure for configuring timer operation control. 8.4.8.6 Response time between EMG pin input and PPG outputs being initialized The time between a low level input being detected on the EMG pin and the PPG outputs being initialized is up to 10/fc [s]. Page 101 8. 10-Bit Timer/Counter (TC7) 8.4 Features TMP86CM27FG Emergency stop input 10/fc [s] 1.25 s (at 8 MHz) Output initialized forcibly PPG pin output Share port in input mode EMGR = 1, protection feature enabled Initial output state EMG pin input Emergency stop input EMGIE EMGF (State monitor) EMG interrupt EMGF = 1, emergency output stop state INTEMG (EMG interrupt) EMGR = 1, cancel emergency output stop state TC7ST TC7ST = 1, timer operating STM = 01, timer operating (Continuous mode) TG7ST = 0 Specified with an instruction STM STM = 00 Emergency output stop state Figure 8-23 Timing between EMG Pin Input being Detected and PPG Outputs being Disabled 8.4.9 TC7 operation and microcontroller operating mode The TC7 operates when the microcontroller is placed in NORMAL1, NORMAL2, IDLE1, or IDLE2 mode. If the mode changes from NORMAL or IDLE to STOP, SLOW, or SLEEP while the TC7 is operating, the TC7 is initialized and stops operating. To change the microcontroller operating mode from NORMAL or IDLE to STOP, SLOW, or SLEEP, ensure that the TC7 timer is stopped before attempting to execute a mode change instruction. To change the mode from STOP, SLOW, or SLEEP to NORMAL to restart the TC7, reconfigure all registers according to the appropriate TC7 operation procedure. Page 102 TMP86CM27FG 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC4 interrupt request fc/2 5 fc/2 fc/23 fs 7 fc/2 fc TC4 pin TC4M TC4S TFF4 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC4S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F4 PDO4/PWM4/ PPG4 pin TC4CK TC4CR TTREG4 PWREG4 PWM, PPG mode DecodeEN TFF4 PDO, PWM, PPG mode 16-bit mode TC3S PWM mode fc/211 or fs/23 fc/27 5 fc/2 3 fc/2 fs TC3 pin TC3M TC3S TFF3 fc/2 fc A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC3 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F3 PDO3/PWM3/ pin TC3CK TC3CR TTREG3 PWREG3 PWM mode DecodeEN TFF3 PDO, PWM mode 16-bit mode Figure 9-1 8-Bit TimerCouter 3, 4 Page 103 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CM27FG 9.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 (001CH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG3 (001AH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG3) setting while the timer is running. Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 3 Control Register TC3CR (0018H) 7 TFF3 6 5 TC3CK 4 3 TC3S 2 1 TC3M 0 (Initial value: 0000 0000) TFF3 Time F/F3 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W 000 001 TC3CK Operating clock selection [Hz] 010 011 100 101 110 111 TC3S TC3 start control 0: 1: 000: 001: TC3M TC3M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 fs fc/2 fc R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC4M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running. Note 3: To stop the timer operation (TC3S= 1 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer operation (TC3S= 0 1), TC3M, TC3CK and TFF3 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR Page 104 TMP86CM27FG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 105 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CM27FG The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 (001DH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG4 (001BH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG4) setting while the timer is running. Note 2: Do not change the timer register (PWREG4) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 4 Control Register TC4CR (0019H) 7 TFF4 6 5 TC4CK 4 3 TC4S 2 1 TC4M 0 (Initial value: 0000 0000) TFF4 Timer F/F4 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 fs fc/2 fc TC4 pin input 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC4CK Operating clock selection [Hz] 010 011 100 101 110 111 TC4S TC4 start control 0: 1: 000: 001: 010: TC4M TC4M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 fs fc/2 fc 3 Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC4M, TC4CK and TFF4 settings while the timer is running. Note 3: To stop the timer operation (TC4S= 1 0), do not change the TC4M, TC4CK and TFF4 settings. To start the timer operation (TC4S= 0 1), TC4M, TC4CK and TFF4 can be programmed. Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC4 overflow signal regardless of the TC3CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR Page 106 TMP86CM27FG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note 2: : Available source clock Table 9-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note2: : Available source clock Page 107 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CM27FG Table 9-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG4, 3) 65535 256 (TTREG4, 3) 65535 2 (PWREG4, 3) 65534 1 (PWREG4, 3) < (TTREG4, 3) 65535 16-bit PPG and (PWREG4, 3) + 1 < (TTREG4, 3) Register Value Note: n = 3 to 4 Page 108 TMP86CM27FG 9.3 Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 9.3.1 8-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 9-4 Source Clock for TimerCounter 3, 4 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - Resolution Repeated Cycle fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns 244.14 s - - - 32.6 ms 2.0 ms 510 s 127.5 s 62.3 ms - - - Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter4, fc = 16.0 MHz) LD DI SET EI LD LD (TC4CR), 00010000B (TC4CR), 00011000B : Sets the operating cock to fc/27, and 8-bit timer mode. : Starts TC4. (EIRH). 5 : Enables INTTC4 interrupt. (TTREG4), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 109 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CM27FG TC4CR Internal Source Clock Counter TTREG4 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-2 8-Bit Timer Mode Timing Chart (TC4) 9.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC4CR Counter TTREG4 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4) 9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 110 TMP86CM27FG Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port LD LD LD (TTREG4), 3DH (TC4CR), 00010001B (TC4CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC4. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 111 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) Match detect Match detect Match detect Page 112 Counter 0 1 2 TTREG4 ? n Match detect Timer F/F4 Set F/F PDO4 pin INTTC4 interrupt request Held at the level when the timer is stopped TMP86CM27FG TMP86CM27FG 9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 9-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc Page 113 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock n Write to PWREG4 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG4 PWREG4 ? Shift Shift m Match detect n m p Shift p Match detect Match detect Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) Page 114 n One cycle period m Shift Shift registar ? n Match detect Timer F/F4 PWM4 pin n p INTTC4 interrupt request TMP86CM27FG TMP86CM27FG 9.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the timer mode, fix TCjCR Table 9-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 - - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns fs = 32.768 kHz 244.14 s - - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms fs = 32.768 kHz 16 s - - - Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC3CR), 13H :Sets the operating cock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRH). 5 : Enables INTTC4 interrupt. (TTREG3), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC4CR), 04H (TC4CR), 0CH TC4CR Internal source clock Counter TTREG3 (Lower byte) TTREG4 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-6 16-Bit Timer Mode Timing Chart (TC3 and TC4) Page 115 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CM27FG 9.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the event counter mode, fix TCjCR 9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 116 TMP86CM27FG CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the PWM4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4 pin during the warm-up period time after exiting the STOP mode. Table 9-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - Resolution fc = 16 MHz 128 s 8 s 2 s 500ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2 s fs = 32.768 kHz 16 s - - - 2s - - 8.2 ms 4.1 ms Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG3), 07D0H (TC3CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC4CR), 056H (TC4CR), 05EH Page 117 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock an Write to PWREG3 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG3 FFFF 0 1 cp PWREG3 (Lower byte) ? Write to PWREG4 n m p Write to PWREG4 Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 118 b Shift Shift bm Match detect an One cycle period bm PWREG4 (Upper byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F4 PWM4 pin an cp INTTC4 interrupt request TMP86CM27FG TMP86CM27FG 9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW LDW LD (PWREG3), 07D0H (TTREG3), 8002H (TC3CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC4CR), 057H (TC4CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 119 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG3 (Lower byte) ? n Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) Page 120 Match detect Match detect Match detect mn mn PWREG4 (Upper byte) ? m Match detect Match detect TTREG3 (Lower byte) ? r TTREG4 (Upper byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F4 PPG4 pin INTTC4 interrupt request TMP86CM27FG TMP86CM27FG 9.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR 9.3.9.1 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz) Maximum Time Setting (TTREG4, 3 = 0100H) 7.81 ms Maximum Time Setting (TTREG4, 3 = FF00H) 1.99 s Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode SET LD LD LD DI SET EI SET : PINTTC4: CLR SET (TC4CR).3 : (TC4CR).3 (SYSCR2).5 : Stops TC4 and 3. : SYSCR2 CLR RETI : VINTTC4: DW (SYSCR2).7 : PINTTC4 : INTTC4 vector table Page 121 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CM27FG 9.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode Minimum time (TTREG4, 3 = 0100H) 16 s Maximum time (TTREG4, 3 = FF00H) 4.08 ms Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode SET LD LD LD (SYSCR2).7 (TC3CR), 63H (TC4CR), 05H (TTREG3), 0F800H : SYSCR2 DI SET EI SET : PINTTC4: CLR CLR CLR (SYSCR2).6 RETI : VINTTC4: DW : PINTTC4 : INTTC4 vector table Page 122 TMP86CM27FG 10. Real-Time Clock The TMP86CM27FG include a real time counter (RTC). A low-frequency clock can be used to provide a periodic interrupt (0.0625[s],0.125[s],0.25[s],0.50[s]) at a programmed interval, implement the clock function. The RTC can be used in the mode in which the low-frequency oscillator is active (except for the SLEEP0 mode). 10.1 Configuration RTCCR Selector RTCSEL RTCRUN 211/fs 212/fs 213/fs 214/fs fs (32.768 kHz) Binary counter Interrupt request INTRTC Figure 10-1 Configuration of the RTC 10.2 Control of the RTC The RTC is controlled by the RTC control register (RTCCR). RTC Control Register RTCCR (002DH) 7 6 5 4 3 2 RTCSEL 1 0 RTCRUN (Initial value: **** *000) RTCSEL Interrupt generation period (fs = 32.768 kHz) 00: 0.50 [s] 01: 0.25 [s] 10: 0.125 [s] 11: 0.0625 [s] 0: Stops and clears the binary counter. 1: Starts counting R/W RTCRUN RTC control Note 1: Program the RTCCR during low-frequency oscillation (when SYSCR2 Page 123 10. Real-Time Clock 10.3 Function TMP86CM27FG 10.3 Function The RTC counts up on the internal low-frequency clock. When RTCCR Page 124 TMP86CM27FG 11. Asynchronous Serial interface (UART ) 11.1 Configuration UART control register 1 UARTCR1 Transmit data buffer TDBUF Receive data buffer RDBUF 3 2 Receive control circuit 2 Transmit control circuit Shift register Shift register Parity bit Stop bit Noise rejection circuit M P X M P X INTTXD RXD0 RXD1 TXD0 TXD1 INTRXD Transmit/receive clock Y S fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 INTTC3 fc/96 A B C D E F G H M P X A B C S 2 fc/26 7 fc/2 8 fc/2 2 Y Counter UARTSR 4 UARTCR2 MULSEL Multi function register MPX: Multiplexer UART status register Baud rate generator UART control register 2 Figure 11-1 UART (Asynchronous Serial Interface) Page 125 11. Asynchronous Serial interface (UART ) 11.2 Control TMP86CM27FG 11.2 Control UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be monitored using the UART status register (UARTSR). TXD pin and RXD pin can be selected a port assignment by Multi Function Register (MULSEL). UART Control Register1 UARTCR1 (0025H) 7 TXE 6 RXE 5 STBT 4 EVEN 3 PE 2 1 BRG 0 (Initial value: 0000 0000) TXE RXE STBT EVEN PE Transfer operation Receive operation Transmit stop bit length Even-numbered parity Parity addition 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 000: 001: 010: 011: 100: 101: 110: 111: Disable Enable Disable Enable 1 bit 2 bits Odd-numbered parity Even-numbered parity No parity Parity fc/13 [Hz] fc/26 fc/52 fc/104 fc/208 fc/416 TC3 ( Input INTTC3) fc/96 Write only BRG Transmit clock select Note 1: When operations are disabled by setting TXE and RXE bit to "0", the setting becomes valid when data transmit or receive complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. Note 2: The transmit clock and the parity are common to transmit and receive. Note 3: UARTCR1 UART Control Register2 UARTCR2 (0026H) 7 6 5 4 3 2 RXDNC 1 0 STOPBR (Initial value: **** *000) RXDNC Selection of RXD input noise rejectio time 00: 01: 10: 11: 0: 1: No noise rejection (Hysteresis input) Rejects pulses shorter than 31/fc [s] as noise Rejects pulses shorter than 63/fc [s] as noise Rejects pulses shorter than 127/fc [s] as noise 1 bit 2 bits Write only STOPBR Receive stop bit length Note: When UARTCR2 Page 126 TMP86CM27FG UART Status Register UARTSR (0025H) 7 PERR 6 FERR 5 OERR 4 RBFL 3 TEND 2 TBEP 1 0 (Initial value: 0000 11**) PERR FERR OERR RBFL TEND TBEP Parity error flag Framing error flag Overrun error flag Receive data buffer full flag Transmit end flag Transmit data buffer empty flag 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: No parity error Parity error No framing error Framing error No overrun error Overrun error Receive data buffer empty Receive data buffer full On transmitting Transmit end Transmit data buffer full (Transmit data writing is finished) Transmit data buffer empty Read only Note: When an INTTXD is generated, TBEP flag is set to "1" automatically. UART Receive Data Buffer RDBUF (0FABH) 7 6 5 4 3 2 1 0 Read only (Initial value: 0000 0000) UART Transmit Data Buffer TDBUF (0FABH) 7 6 5 4 3 2 1 0 Write only (Initial value: 0000 0000) Multi Function Register MULSEL (0FBBH) 7 6 5 4 3 2 1 (SIO SEL) 0 UART SEL (Initial value: **** **00) UARTSEL UART function pins select 0: 1: P01 (TXD0), P00 (RXD0) P43 (TXD1), P37 (RXD1) R/W Note 1: Do not change MULSEL Page 127 11. Asynchronous Serial interface (UART ) 11.3 Transfer Data Format TMP86CM27FG 11.3 Transfer Data Format In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1 PE STBT 1 Start 2 Bit 0 3 Bit 1 Frame Length 8 Bit 6 9 Bit 7 10 Stop 1 11 12 0 0 1 1 0 1 0 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Stop 2 Figure 11-2 Transfer Data Format Without parity / 1 STOP bit With parity / 1 STOP bit Without parity / 2 STOP bit With parity / 2 STOP bit Figure 11-3 Caution on Changing Transfer Data Format Note: In order to switch the transfer data format, perform transmit operations in the above Figure 11-3 sequence except for the initial setting. Page 128 TMP86CM27FG 11.4 Transfer Rate The baud rate of UART is set of UARTCR1 Source Clock BRG 16 MHz 000 001 010 011 100 101 76800 [baud] 38400 19200 9600 4800 2400 8 MHz 38400 [baud] 19200 9600 4800 2400 1200 4 MHz 19200 [baud] 9600 4800 2400 1200 600 When TC3 is used as the UART transfer rate (when UARTCR1 11.5 Data Sampling Method The UART receiver keeps sampling input using the clock selected by UARTCR1 RXD pin Start bit RT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (a) Without noise rejection circuit Bit 0 RXD pin Start bit RT0 1 2 3 4 5 6 7 8 Bit 0 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (b) With noise rejection circuit Bit 0 Figure 11-4 Data Sampling Method Page 129 11. Asynchronous Serial interface (UART ) 11.6 STOP Bit Length TMP86CM27FG 11.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1 11.7 Parity Set parity / no parity by UARTCR1 11.8 Transmit/Receive Operation 11.8.1 Data Transmit Operation Set UARTCR1 11.8.2 Data Receive Operation Set UARTCR1 Note:When a receive operation is disabled by setting UARTCR1 Page 130 TMP86CM27FG 11.9 Status Flag 11.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR RXD pin Parity Stop Shift register UARTSR xxxx0** pxxxx0* 1pxxxx0 After reading UARTSR then RDBUF clears PERR. INTRXD interrupt Figure 11-5 Generation of Parity Error 11.9.2 Framing Error When "0" is sampled as the stop bit in the receive data, framing error flag UARTSR RXD pin Final bit Stop Shift register UARTSR xxx0** xxxx0* 0xxxx0 After reading UARTSR then RDBUF clears FERR. INTRXD interrupt Figure 11-6 Generation of Framing Error 11.9.3 Overrun Error When all bits in the next data are received while unread data are still in RDBUF, overrun error flag UARTSR Page 131 11. Asynchronous Serial interface (UART ) 11.9 Status Flag TMP86CM27FG UARTSR RXD pin Final bit Stop Shift register RDBUF xxx0** yyyy xxxx0* 1xxxx0 UARTSR After reading UARTSR then RDBUF clears OERR. INTRXD interrupt Figure 11-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UARTSR 11.9.4 Receive Data Buffer Full Loading the received data in RDBUF sets receive data buffer full flag UARTSR RXD pin Final bit Stop Shift register RDBUF xxx0** yyyy xxxx0* 1xxxx0 xxxx After reading UARTSR then RDBUF clears RBFL. UARTSR INTRXD interrupt Figure 11-8 Generation of Receive Data Buffer Full Note:If the overrun error flag UARTSR 11.9.5 Transmit Data Buffer Empty When no data is in the transmit buffer TDBUF, UARTSR Page 132 TMP86CM27FG Data write TDBUF Data write xxxx yyyy zzzz Shift register TXD pin *****1 1xxxx0 *1xxxx Bit 0 ****1x Final bit *****1 Stop 1yyyy0 Start UARTSR INTTXD interrupt Figure 11-9 Generation of Transmit Data Buffer Empty 11.9.6 Transmit End Flag When data are transmitted and no data is in TDBUF (UARTSR Shift register TXD pin ***1xx ****1x *****1 1yyyy0 *1yyyy Stop Data write for TDBUF Start Bit 0 UARTSR UARTSR INTTXD interrupt Figure 11-10 Generation of Transmit End Flag and Transmit Data Buffer Empty Page 133 11. Asynchronous Serial interface (UART ) 11.9 Status Flag TMP86CM27FG Page 134 TMP86CM27FG 12. Synchronous Serial Interface (SIO) The TMP86CM27FG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. Serial interface is connected to outside peripherl devices via SO, SI, SCK port. 12.1 Configuration SIO control / status register SIOSR SIOCR1 SIOCR2 CPU Control circuit Buffer control circuit Shift register Shift clock Transmit and receive data buffer (8 bytes in DBR) 7 6 5 4 3 2 1 0 SO Serial data output 8-bit transfer 4-bit transfer SI Serial data input INTSIO interrupt request Serial clock SCK Serial clock I/O Figure 12-1 Serial Interface Page 135 12. Synchronous Serial Interface (SIO) 12.2 Control TMP86CM27FG 12.2 Control The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be determined by reading SIO status register (SIOSR). The transmit and receive data buffer is controlled by the SIOCR2 SIOCR1 (0FA8H) 7 SIOS 6 SIOINH 5 4 SIOM 3 2 1 SCK 0 (Initial value: 0000 0000) SIOS Indicate transfer start / stop 0: 1: 0: 1: 000: 010: Stop Start Continuously transfer Abort transfer (Automatically cleared after abort) 8-bit transmit mode 4-bit transmit mode 8-bit transmit / receive mode 8-bit receive mode 4-bit receive mode Write only SIOINH Continue / abort transfer SIOM Transfer mode select 100: 101: 110: Except the above: Reserved NORMAL1/2, IDLE1/2 mode DV7CK = 0 000 001 SCK Serial clock select 010 011 100 101 110 111 fc/213 fc/28 fc/27 fc/26 fc/25 fc/24 DV7CK = 1 fs/25 fc/28 fc/27 fc/26 fc/25 fc/24 Reserved External clock ( Input from SCK pin ) SLOW1/2 SLEEP1/2 mode fs/25 Write only Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz] Note 2: Set SIOS to "0" and SIOINH to "1" when setting the transfer mode or serial clock. Note 3: SIOCR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. SIO Control Register 2 SIOCR2 (0FA9H) 7 6 5 4 WAIT 3 2 1 BUF 0 (Initial value: ***0 0000) Page 136 TMP86CM27FG Always sets "00" except 8-bit transmit / receive mode. 00: WAIT Wait control 01: 10: 11: 000: 001: 010: BUF Number of transfer words (Buffer address in use) 011: 100: 101: 110: 111: Tf = TD(Non wait) Tf = 2TD(Wait) Tf = 4TD(Wait) Tf = 8TD (Wait) 1 word transfer 2 words transfer 3 words transfer 4 words transfer 5 words transfer 6 words transfer 7 words transfer 8 words transfer 0FA0H 0FA0H ~ 0FA1H 0FA0H ~ 0FA2H 0FA0H ~ 0FA3H 0FA0H ~ 0FA4H 0FA0H ~ 0FA5H 0FA0H ~ 0FA6H 0FA0H ~ 0FA7H Write only Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving. Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest address. ( The first buffer address transmitted is 0FA0H ). Note 3: The value to be loaded to BUF is held after transfer is completed. Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0). Note 5: *: Don't care Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. SIO Status Register SIOSR (0FA9H) 7 SIOF 6 SEF 5 4 3 2 1 0 SIOF SEF Serial transfer operating status monitor Shift operating status monitor 0: 1: 0: 1: Transfer terminated Transfer in process Shift operation terminated Shift operation in process Read only Note 1: Tf; Frame time, TD; Data transfer time Note 2: After SIOS is cleared to "0", SIOF is cleared to "0" at the termination of transfer or the setting of SIOINH to "1". (output) SCK output TD Tf Figure 12-2 Frame time (Tf) and Data transfer time (TD) Multi Function Register MULSEL (0FBBH) 7 6 5 4 3 2 1 SIOSEL 0 (UARTSEL) (Initial value: **** **00) SIOSEL SIO function pins select 0: 1: P05 (SI0), P06 (SO0), P07 (SCK0) P40 (SI1), P41 (SO1), P42 (SCK1) R/W Note 1: Do not change MULSEL Page 137 12. Synchronous Serial Interface (SIO) 12.3 Serial clock TMP86CM27FG Note 2: Set MULSEL register before performing the setting terminal of a I/O port when changing a terminal. 12.3 Serial clock 12.3.1 Clock source Internal clock or external clock for the source clock is selected by SIOCR1 12.3.1.1 Internal clock Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The SCK pin goes high when transfer starts. When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. Table 12-1 Serial Clock Rate NORMAL1/2, IDLE1/2 mode DV7CK = 0 SCK 000 001 010 011 100 101 110 111 Clock fc/2 13 DV7CK = 1 Baud Rate 1.91 Kbps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps External Clock fs/2 5 SLOW1/2, SLEEP1/2 mode Baud Rate 1024 bps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps External Clock fs/2 External 5 Baud Rate 1024 bps External fc/28 fc/27 fc/26 fc/25 fc/24 External fc/28 fc/27 fc/26 fc/25 fc/24 External Note: 1 Kbit = 1024 bit (fc = 16 MHz, fs = 32.768 kHz) Automatically wait function SCK pin (output) SO pin (output) Written transmit data a a0 a1 a2 a3 b b0 b1 c b2 b3 c0 c1 Figure 12-3 Automatic Wait Function (at 4-bit transmit mode) 12.3.1.2 External clock An external clock connected to the SCK pin is used as the serial clock. In this case, output latch of this port should be set to "1". To ensure shifting, a pulse width of at least 4 machine cycles is required. This pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the program. Therfore, maximum transfer frequency will be 488.3K bit/sec (at fc=16MHz). Page 138 TMP86CM27FG SCK pin (Output) tSCKL tSCKH tcyc = 4/fc (In the NORMAL1/2, IDLE1/2 modes) 4/fs (In the SLOW1/2, SLEEP1/2 modes) tSCKL, tSCKH > 4tcyc Figure 12-4 External clock pulse width 12.3.2 Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. 12.3.2.1 Leading edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/ output). 12.3.2.2 Trailing edge Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output). SCK pin SO pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register 3210 *321 **32 ***3 (a) Leading edge SCK pin SI pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register **** 0*** 10** 210* 3210 *; Don't care (b) Trailing edge Figure 12-5 Shift edge 12.4 Number of bits to transfer Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. The upper 4 bits are cleared to "0" when receiving. The data is transferred in sequence starting at the least significant bit (LSB). 12.5 Number of words to transfer Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred can be selected by SIOCR2 12. Synchronous Serial Interface (SIO) 12.6 Transfer Mode TMP86CM27FG An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of words is to be changed during transfer, the serial interface must be stopped before making the change. The number of words can be changed during automatic-wait operation of an internal clock. In this case, the serial interface is not required to be stopped. SCK pin SO pin a0 a1 a2 a3 INTSIO interrupt (a) 1 word transmit SCK pin SO pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (b) 3 words transmit SCK pin SI pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (c) 3 words receive Figure 12-6 Number of words to transfer (Example: 1word = 4bit) 12.6 Transfer Mode SIOCR1 12.6.1 4-bit and 8-bit transfer modes In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data (number of transfer words to be transferred) to the data buffer registers (DBR). After the data are written, the transmission is started by setting SIOCR1 Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do not use the DBR of the remained 5 words. Page 140 TMP86CM27FG When an external clock is used, the data must be written to the data buffer register before shifting next data. Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. The transmission is ended by clearing SIOCR1 Clear SIOS SIOCR1 SIOSR |